Cadence reveal 14nm Test-chip featuring ARM Cortex-M0 processor and IBM FinFET Process Technology

The 14-nanometer ecosystem and chip are significant milestones of a multi-year agreement between ARM, Cadence and IBM to develop systems-on-chip (SoCs) at the advanced process nodes of 14 nanometers and beyond. SoCs designed at 14 nanometers with FinFET technology offer the promise of a significant reduction in power consumption.

This chip represents a major milestone for advanced node process technology, achieved through tight collaboration among experts at the three companies,” said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “FinFET designs offer significant advantages to the design community, but also require advanced foundry support, IP and EDA technology to meet the considerable challenges. Cadence, IBM and ARM are collaborating to address these challenges and develop an ecosystem that can support 14-nanometer FinFET development for a broad range of production designs.”

The chip was developed to validate the building blocks of foundation IP for 14-nanometer design. In addition to the ARM processor, SRAM memory blocks and other blocks were included that provide the characterization data necessary for foundation IP development for FinFET-based ARM Artisan physical IP.

“Each move to smaller geometry brings new challenges that require deep collaboration among ecosystem leaders in the SoC design chain,” said Dipesh Patel, vice president and general manager, Physical IP Division at ARM. “With 14-nanometer design, many of these challenges center on FinFETs, and our work with Cadence and IBM has focused on answering the key questions about how to make 14-nanometer FinFET design viable and economically feasible.”

ARM design engineers incorporated an ARM Cortex-M0 processor using 14-nanometer FinFET technology built on IBM’s silicon-on-insulator (SOI) technology, which offers an optimal performance/power profile. A comprehensive 14-nanometer double patterning and FinFET support methodology was employed, with engineers using Cadence technology to design the FinFET 3D transistor chip.

“The tapeout of this 14-nanometer test chip is the culmination of the significant progress we have made with FinFET on SOI utilizing it's built in dielectric isolation,” said Gary Patton, vice president of IBM Semiconductor Research and Development Center. “In fact, Cadence and ARM have collaborated on a design solution to tape out this test chip based on IBM’s FinFET technology. We continue to collaborate to deliver on the promise of superior power, performance, and variability control of fully depleted SOI FinFET devices at 14 nanometers and beyond.”

To succeed, engineers required support for 14-nanometer and FinFET rule decks, as well as enhanced timing analysis. The chip was implemented using the Cadence Encounter Digital Implementation (EDI) System with ARM 8-track 14-nanometer FinFET standard cell libraries designed with Cadence Virtuoso tools. EDI System provides advanced digital capability required for implementing designs based on 14-nanometer FinFET-based DRC rules, and incorporates new GigaOpt optimization technology to realize power and performance benefits offered by FinFET technology. In addition, the solution also uses production-proven double patterning-correct implementation capabilities. Encounter Power System, Encounter Timing System and Cadence QRC Extraction provide 14nm timing and power signoff capabilities supporting 14-nanometer FinFET structures.