ARM Announces AMBA 5 CHI Specification to Enable High Performance, Highly Scalable SoC Technology

Building on the success of AMBA 4 ACE technology, the AMBA 5 CHI specification has been developed by ARM with the participation of leading industry players including ARM semiconductor partners, third party IP providers and the EDA industry. The AMBA 5 CHI protocol is used by the ARMv8 architecture-based Cortex-A57 and Cortex-A53 processors and the CoreLink DMC-520 Dynamic Memory Controller. It is also used by the CoreLink CCN-504 Cache Coherent Network, which is capable of 1 Terabit/s data flows.

AMBA 5 CHI has been developed to support high frequency, non-blocking data transfers between multiple fully coherent processors. The interface ensures optimal system performance by supporting distributed level 3 caches, very high rates of I/O coherent communication, and Quality of Service (QoS) functionality. The AMBA 5 CHI architecture also introduces a layered model to allow implementations to separate communication and transport protocols, which enables the optimal trade-off between performance, power and area. More information on the AMBA CHI specification can be found here

“To ensure that our silicon partners can rapidly deploy IP and SoCs implementing the AMBA 5 CHI protocol, ARM has worked closely with many partners across the SoC design ecosystem,” says Noel Hurley, vice president, Marketing and Strategy, Processor Division, ARM. “Through early engagement we have enabled our EDA partners to develop a wide range of verification IP, and debugging and performance analysis tools to accelerate the implementation of AMBA 5 CHI based SoCs.”

“As part of our longstanding relationship with ARM, Cadence is developing verification IP that speeds customer adoption of the new AMBA 5 CHI specification,” said Martin Lund, senior vice president, Research and Development, SoC Realization Group at Cadence. “The Cadence VIP will offer unique features to enable our mutual customers to optimize performance while speeding development of multi-core SoCs.”

As the market and technology leader in formal verification, and long-time solution provider to ARM's internal engineering teams, we were glad to be called upon to help validate the AMBA 5 CHI protocol and to develop the first fully-correlated AMBA 5 CHI Verification IP, now available for simultaneous release, said Kathryn Kranen, CEO of Jasper Design Automation. As in prior collaboration efforts, ARM and Jasper are maximizing the ability of our mutual customers to leverage the latest protocol in low power, high-performance compute systems.

“Mentor is proud to be one of ARM’s lead partners for the verification of the AMBA 5 CHI coherent hub interface architecture,” said Walden Rhines, Chairman and Chief Executive Officer of Mentor Graphics. “Our close collaboration with ARM makes it possible for their customers to maximize the performance of complex interconnect and cache coherent subsystems. Our joint work on AMBA 5 CHI has shown the advantages of seamlessly supporting both simulation and emulation as a cohesive platform.”

“Through more than 15 years of R&D collaboration, ARM and Synopsys have successfully delivered design and verification solutions, including SystemVerilog, verification methodology, simulation performance, low power verification, debug, interface IP and most recently our verification IP for AMBA 4 AXI4 ACE interconnect,” said Manoj Gandhi, senior vice president and general manager of the Synopsys Verification Group. ”Through our collaboration on the AMBA 5 standard, Synopsys plans to provide verification IP with simulation, emulation, debug, performance analysis, and support the AMBA 5 interconnect with our interface IP to accelerate the development of advanced SoCs.”

The AMBA 5 CHI specification and associated protocol checkers (SystemVerilog assertions) are available, at no cost, under license to companies integrating or developing IP that implements the AMBA 5 CHI protocol.