/> Qsys uses a NoC-based interconnect to deliver higher performance systems compared to conventional bus and switch fabric architectures. To demonstrate the capabilities of the high-performance interconnect in version 11.0, Altera offers a PCIe® to DDR3 reference design built using Qsys. The reference design achieves throughput of over 1,400MB/s between a memory-mapped PCIe Gen2 x4 Endpoint and an external DDR3 memory. The design uses an automatically pipelined, NoC-based interconnect to packetize data for easier and faster transport. The reference design demonstrates how an Altera-provided PCIe IP core saves months of development time by eliminating the need to develop Transaction Layer Packet (TLP) encoding/decoding logic and by simplifying PCIe protocol interface complexity. Customers can download the reference design from the Qsys page of Altera's Web site at www.altera.com/qsys.

Qsys enables designers to develop large, scalable systems with a hierarchical design flow feature. Using hierarchy, designers can divide large FPGA designs that include a high number of IP cores or system components into smaller sub-systems. The hierarchical design flow in Qsys allows designers to easily manage each sub-system while giving them the ability to add additional sub-systems to the design with minimal impact on system performance.

Qsys delivers the highest flexibility by automatically handling the bridging between multiple interface standards. Designers leveraging Qsys can develop systems using Avalon-based, Qsys-compliant IP cores, and can add IP cores that use a different industry standard interface in the future without replacing the original IP cores. Qsys supports the open-standard Avalon interface with this release. Future releases of Qsys will support additional industry-standard interfaces, such as AMBA AXI from ARM.

“Customer adoption of the beta release of Qsys exceeded our expectations and we are pleased to offer the production release today,” said Chris Balough, senior director of software, embedded, and digital signal processing (DSP) marketing at Altera. “Customers using Qsys will see firsthand the productivity benefits the tool provides, including higher system performance, improved system scalability and faster development with the memory mapped PCIe IP core.

Quartus II software version 11.0 provides faster board bring up through enhancements to the software's external memory interface toolkit and transceiver toolkit. New performance and monitoring capabilities in the external memory interface toolkit improves productivity by helping achieve maximum memory efficiency. The enhanced transceiver toolkit delivers an improved channel manager interface and an updated transceiver control panel, so designers can optimize their transceivers for improved signal integrity and bring their boards up faster.