Altera Unveils 28-nm Device Portfolio Tailored to Customers’ Diverse Design Requirements

As a result of its long history of close partnerships with industry-leading customers, Altera has a deep understanding of the unique performance, feature, and power requirements necessary across a wide range of applications from the highest bandwidth to the lowest power. With this 28-nm portfolio, Altera leverages advantages in transceiver technology, product architecture, intellectual property (IP) integration, and process technology to optimize solutions that address the diverse design challenges of each of its customers. Altera is tailoring these advantages for diversification in the following ways:



* Transceivers—Altera optimized its industry-leading and proven transceiver technology for each 28-nm device family performance range. Altera's 28-nm devices support transceiver speeds from 600 Mbps to 28 Gbps.

* Product architecture—On-chip memories optimized for performance and efficiency; hard and soft memory controllers to support the necessary application bandwidth, power and cost requirements; and high-end, midrange and low-cost I/Os optimized for performance.

* IP integration—To meet customers' cost, power and performance requirements, Altera is hardening a range of system-level IP, such as PCI Express® (PCIe®) Gen2 x1 and x4, PCIe Gen3 x8, Interlaken, 40G/100G and 100 Gigabit Ethernet (100GbE).

* Process technology—To effectively serve the broadest range of applications, Altera is utilizing TSMC's 28-nm High Performance (28HP) process technology for its high-end product family (Stratix V FPGAs) and HardCopy V ASICs, and TSMC's 28-nm Low-Power (28LP) process technology for use in its low-cost (Cyclone V FPGAs) and midrange (Arria V FPGAs) product families. The 28LP process also enables Altera to deliver an optimal balance of cost, performance and low power. The use of 28HP process technology at the high end is critical in delivering the core and transceiver performance required by high-end applications.



For applications such as motor control, displays and software-defined radios, where low power and board space are concerns, Altera's Cyclone V FPGA family is an ideal fit. The Cyclone V family offers 40 percent lower total power versus the previous generation devices, 12 transceivers operating at up to 5 Gbps, hardened PCIe Gen2 x1 blocks, and hard memory controllers supporting LPDDR2, mobile DDR and DDR3 external memory. For more detailed information on the Cyclone V family, visit www.altera.com/cyclonev.



Targeting applications that require a balance of cost, low power and high performance, such as remote radio units, in-studio mixers and 10G/40G linecards, Altera is unveiling its Arria V FPGA family. Offering 40 percent lower total power versus previous generation devices, the Arria V FPGA family devices include transceivers operating at up to 10 Gbps, hard memory controllers supporting DDR3 external memory, and efficient systolic finite impulse response (FIR) filters with variable-precision DSP blocks. For more detailed information on the Arria V family, visit www.altera.com/arriav.



The Stratix V FPGA family addresses a broad range of high-bandwidth applications such as advanced LTE basestations, high-end RF cards and military radar. Altera has expanded the capabilities of the Stratix V family to support evolving market needs. The maximum transceiver data rates in Stratix V GX FPGAs were increased to 14.1 Gbps to support emerging high-speed protocols, including 16G Fibre Channel (16GFC). Additionally the density of the Stratix V GX FPGA was increased to 1.1 million logic elements (LEs) in a monolithic die, to provide customers even higher levels of integration. For more information on the Stratix V family, visit www.altera.com/stratixv.



HardCopy V ASICs extend Altera's leadership in low-nonrecurring-engineering (NRE), low-risk transceiver-based ASICs. Compared to previous HardCopy ASIC devices, HardCopy V ASICs deliver higher performance for transceivers, I/Os, and core logic; with higher levels of logic and memory integration. With these new capabilities, HardCopy V ASICs now support a wider range of high-volume applications which require low power, lower unit cost, or improved single-event upset (SEU) tolerance in production.



Addressing customers' desire for increased design productivity, Altera's 28-nm device portfolio will be supported by its Quartus® II development software, the programmable logic industry's number-one software in performance and productivity for CPLD, FPGA and HardCopy ASIC design. The Quartus II software's new Qsys system-level integration tool simplifies IP integration and offers access to the industry's broadest offering embedded processor options, including a hardened ARM® Cortex™-A9 MPCore™.



“Altera recognizes that every design is unique and customers are looking for solutions that deliver the right set of features and performance levels that meet their specific needs and still offer the ability to differentiate,” said Vince Hu, vice president, product and corporate marketing at Altera. “With its 28-nm portfolio, Altera is leveraging its ongoing investment in key areas, such as transceiver design, system-level IP, design tools, and process optimization with TSMC, to create the industry's broadest set of solutions.”