Design

Agilent Technologies' New GoldenGate Release 4.4 Accelerates Advanced Node CMOS RFIC Design

9th December 2009
ES Admin
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Agilent has announced the release of its RFIC simulation, verification and analysis software -- GoldenGate version 4.4. This release extends Agilent's leadership in advanced node RFIC design with enhanced performance, new key stability and yield analyses, and RF extensions to mixed-signal simulation. In addition, the new release brings performance and flexibility updates to its unique wireless standards-based virtual test bench capability.
Agilent has announced the release of its RFIC simulation, verification and analysis software -- GoldenGate version 4.4. This release extends Agilent's leadership in advanced node RFIC design with enhanced performance, new key stability and yield analyses, and RF extensions to mixed-signal simulation. In addition, the new release brings performance and flexibility updates to its unique wireless standards-based virtual test bench capability.

Advanced node RFIC design makes you rethink what's important from a simulation point of view, said Paul Colestock, product planning and marketing manager with Agilent's EEsof EDA organization. GoldenGate version 4.4 delivers improvements for just about every important aspect of RFIC design in advanced CMOS technology nodes.

Agilent's GoldenGate version 4.4 delivers the following updates to key RF design analyses:

* performance enhancements for advanced node RFIC designs, including a 2x improvement in speed for periodic steady state (harmonic balance) analysis, a new single-sideband noise option, and fast envelope support for wireless virtual test benches;
* periodic steady-state based stability analysis that finds instabilities under large signal conditions for oscillators and driven RF circuits, even with large extracted views; and
* a fast yield contributor analysis that quickly determines circuit yield contributors at any stage of the RFIC design flow -- something not possible with traditional Monte Carlo methods -- allowing designers to gain insight, improve yield and save time by optimizing only what really matters.

Improvements in wireless design verification include:

* comprehensive wireless test bench flow that links system and RF simulation for verification of RFICs;
* analog mixed-signal co-simulation with GoldenGate to accelerate RF-mixed-signal simulations with support for envelope transient analysis with Verilog-AMS;
* RF and package co-design that verifies RFICs with package- and board-level RF passives using more than 150 new components in the Agilent Advanced Design System passive RF component library for GoldenGate; and
* cost effective parallel licensing option for parallel sweep simulation tasks.

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