OpenHW Group Sets RISC-V Quality Standard

This marks the first of many projects based on the CV32E40P, which was verified using the Imperas RISC-V golden reference model; now in development both within open-source community projects and commercial designs.

Imperas is a founding member of the OpenHW Group which was established with an objective to drive the adoption of open-source hardware by delivering IP cores based on industrial strength verification and compatibility with the established commercial EDA design tools and flows. The use of the Imperas lock-step-compare methodology for the verification of the CV32E40P sets the standard for quality verification for RISC-V processor cores, not just open-source IP.

As an open standard Instruction Set Architecture (ISA) RISC-V is a natural option for open-source hardware projects. The RISC-V specifications are based on a modular framework with many standard extensions, each with significant options and configuration flexibility. All the design flexibility of RISC-V increases the requirements for extensive verification plans, including full dynamic operations with asynchronous events and debug modes of operation. The OpenHW Verification Task Group set up the CORE-V-VERIF verification testbench to verify not just the core, but with the built-in flexibility to accommodate future adopters as they extend the base core features and the associated test requirements.

To help leverage the investment in verification IP and test infrastructure, the open standard RISC-V Verification Interface (RVVI) has been adopted for OpenHW CORE-V projects to support the roadmap of IP cores. RVVI provides a common methodology for the key components of the testbench to connect the RTL instruction trace and reference models to fully support the lock-step-compare comparisons. The RVVI flexibility supports the full range of RISC-V specifications and features and can be adopted with increasing levels of complexity for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, plus user-defined custom instructions and extensions. RVVI supports the innovation of RISC-V with the flexibility required for verification IP and reuse as DV teams scale up to support the rapid growth in RISC-V verification projects.

“The open RISC-V ISA specification is an excellent starting point and open-source processor IP cores, such as the CORE-V family, have real potential to change the industry,” said Rick O’Connor, President & CEO OpenHW Group.

“OpenHW is determined to provide high-quality open-source hardware IP compatible with the established EDA tools and flows for adoption in commercial designs,” said Simon Davidmann, CEO at Imperas Software “The CV32E40P as the first IP core to be completed in the CORE-V-VERIF flow marks not just the completion of a project, but the start of the era when open-source cores can be adopted in commercial designs without compromise. Research may well drive some aspects of innovation, but quality verification drives adoption.”