Last year, Sondrel launched its Architecting the Future series covering the SFA 100 to the SFA 350A. These pre-packaged, System on chip IP architectures provide a fast track for designing a new chip as all that is needed is to select the most suitable foundry and process, third-party IP and to integrate any of the customer’s own IP to create a custom solution.

Some companies in the chip industry feel that the best practice is to manage the manufacturing supply chain for their chips themselves, i.e., all the many stages that happen after a design is taped out.

The Automotive Industry is setting ever tougher targets for ‘Zero Defects’ in chips because of the need for ultra-high levels of reliability and safety in cars. ‘Zero Defects’ is industry shorthand for the acceptable level of defects and Sondrel, who provides turnkey ASIC design and manufacturing for automotive companies, reports that their specifications are moving from defects per million (DPM) to defects per billion (DP...

As chip supply chains consist of a series of different subcontractors each independently doing a specific task, disconnects can easily happen between them. Sondrel calls these Communication Chasms and warns that they can cause issues that ripple through the rest of the chain adding delays and unexpected costs as stages have to be rescheduled.

The shrinking of nodes means that chips are becoming ever more complex and require ever larger teams of engineers. To ensure that the design time of a chip does not increase as well, Sondrel invests heavily into R&D to create novel modelling tools and flows to streamline the production of ASICs. Sondrel has codified this into its ten steps required to design an SoC architecture.

The ever-increasing processing power of electronic devices means that they are changing from being helpers to being decision makers. So, it is vital that the system does exactly what it was programmed to do for a given situation. Compliance with this is known as Functional Safety (FuSa) and this is increasingly important for many application areas where AI is making critical decisions, and specifically ISO 26262 in the case of automotive.

Edge digital ASIC design becomes more complex every year needing teams of dozens of people working on all the different aspects of it. According to Sondrel, who specialises in these advanced chip designs, there is a growing need for Systems Architects who coordinate every aspect of a design project, hence the company is actively recruiting for specialists with the skill sets that can do this.

Sondrel has revealed its family of Architecting the future IP platforms are easy to modify to precisely match customers’ ASIC requirements.

Bringing a new chip to the automotive market can be daunting due to the high safety standards required - ISO 26262. Sondrel has made this much easier for customers with the launch of its new, quad-channel, IP reference platform that has been architected with ISO26262 applications and the fast integration of customer IP in mind from the start. 

The success of so many SoCs rests in their ability to process huge amounts of data or signals efficiently turning raw data into knowledge. The latest addition to Sondrel’s family of reference IP platforms is a semi-custom SoC design to which a customer’s IP is added to create a bespoke solution for high performance data processing.

Sondrel has announced heavy investment in R&D. The company invests a significant part of its annual budget on R&D programmes to create new and better ways to manage the process of chip design.

Sondrel has announced the second in its family of reference designs for ASICs that provide a framework to support a customer’s own IP, which results in a faster time to market and lower risk. The SFA250A is aimed at Functional Safety (FuSa) applications such as Advanced Driver Assistance Systems (ADAS) and contains an independent FuSa monitor compliant to ISO 26262 ASIL D - ASIC Safety Subsystem (ASS).

Sondrel is designing its first radiation-hard (Rad-Hard) chip for a customer which is due to tape out shortly. The satellite modem will be used in communication satellites and therefore has to be able to withstand the challenges of the high levels of ionising radiation found in orbit that can cause glitches.

Sondrel has expanded its European team with Pascal Cintract, as its Regional Sales Director for Central and Southern Europe.

Israel is a hot bed of innovation, with many technology companies having offices there, along with a very strong start-up culture. As this means there is a greater demand for ASIC design resources than can be met locally, Sondrel has appointed Redtree Solutions as its local representative for its design services.

Sondrel has launched a family of reference designs that could reduce design costs, risk and time by up to 30% compared to starting from scratch. The company has drawn on its experience of designing hundreds of ASICs to create a set of key reference designs that each provide a fast design time for high growth markets.

The sudden need of setting up staff to work from home due to COVID-19 lockdowns presented many challenges for companies around the world. Sondrel, however, had sorted these several years earlier to ensure that all its staff could work flexibly and securely from home. As a result, business is booming and it is now actively seeking over 100 new engineers for its offices around the world.

As more and more foundries are offering 5nm, Sondrel has announced that it is supporting them with 5nm design work. This builds on it being one of the few design houses to have taped out a number of 7nm designs.

Because Sondrel offers a full turnkey service of ASIC production from design through to shipping silicon, it knows what is happening with services at every stage of the manufacturing and test process. The company has noticed increased lead times for SoC package design and manufacturing, particularly for flip chip BGAs that could impact the overall project timelines.

Sondrel has announced the tape-out of its largest chip design for a customer. This has taken a team of up to 200 engineers working on it simultaneously at times to design the 500 square millimetre chip that has over 30 billion transistors, 40 million flipflops, and 23 thousand pads for I/O, power and ground.