The proliferation of smart devices and the IoT has raised concerns amongst developers over protecting their devices from attacks. Gartner has recently predicted that over six billion internet connected ‘things’ will be in use in 2016 - a 30% increase over 2015. Christopher Hallinan from Mentor Graphics explains.

Mentor Graphics Corporation has announced the Mentor Automotive A2B Analyser, the industry’s first third-party development platform supporting the Automotive Audio Bus (A2B) technology developed by Analog Devices. As automotive design complexity continues to grow, OEMs and suppliers are challenged with integrating faster, more efficient technologies into the automotive architecture at lower system costs.

Imagination Technologies has deployed the Veloce emulation platform’s virtualised testbench acceleration (TBX) technology in their internal verification flow for their PowerVR Wizard GR6500, a ray-tracing-enabled GPU. Imagination’s PowerVR Wizard architecture raises the bar for ray-traced graphics in consumer and mobile products, delivering amazing realism and performance while meeting strict power budgets and cost constraints.

New tools are now available from Mentor Graphics that deliver integrated electrical/electronic/software systems engineering capability for the transportation market. The Capital Systems tools allow implementations to be optimised for key parameters such as cost and weight. Unlike other approaches, engineers within the various disciplines do not need to understand one another’s detailed syntax.

The Calibre nmDRC and Calibre nmLVS products from Mentor Graphics have been selected by Xiamen San’an Integrated Circuit as its golden sign-off physical verification solution for gallium arsenide (GaAs) ICs used in mobile and other wireless applications.

Mentor Graphics has announced that the Veloce emulation platform, specifically the Codelink offering, now supports the debug of designs built with AndesCore processors, such as N10 and N13. Andes Technology Corporation is a leading Asia-based supplier of small, low-power, high performance 32-bit embedded CPU cores. Over 600m SoCs containing its CPU cores have been shipped by Andes customers.

Mentor Graphics has announced that Terminus Technology has selected the Mentor Analogue FastSPICE (AFS) Platform for verification and device noise analysis of its data converter, power management, Wireless LAN, high-speed I/O and PLL circuits.

Mentor Graphics has announced that it is collaborating with GLOBALFOUNDRIES to qualify the Mentor RTL to GDS platform. This is to include the RealTime Designer physical RTL synthesis solution and Olympus-SoC place & route system, for the current version of the GLOBALFOUNDRIES 22FDX platform reference flow.

Mentor Graphics Corporation has announced the availability of the Vista virtual platforms for the Arria 10 SoC FPGA. The Vista virtual platforms are fully functional simulation models of processor subsystems and peripherals offered as freely downloadable pre-built binaries. These accelerate embedded software development across the entire product life cycle for significant time-to-market and product development cost savings.

Mentor Graphics has announced the availability of the Mentor Automotive Safety Certifiable Digital Instrument Cluster solution enabling safety-critical driver information to be displayed simultaneously with rich 3D graphics on a single instrument cluster display. The software architecture is implemented on a multi-core and even on single-core SoC and features very fast boot time.

Providing visualisation, placement and design rule checking in 3D, Mentor Graphics has announced new PADS 3D tool capabilities plus major usability enhancements to the PADS flow for PCB design. This minimises iterations with mechanical and manufacturing teams while schematic design and layout enhancements improve usability across the flow for increased user productivity.

Mentor Graphics has announced the Veloce VirtuaLAB Ethernet environment with support for 25, 50 and 100G Ethernet. This support enables highly efficient, emulation-based verification for the massive Ethernet-based designs being created today.

Mentor Graphics has announced a new version of its ODB++ intelligent product model, a single and open data structure for transferring PCB designs into data for fabrication, assembly and test. The version 8.1 of the ODB++ product model format provides a unique virtual documentation capability which seamlessly translates all data files, drawings, and documents from PCB design through the manufacturing flow.

Mentor Graphics has announced that speciality foundry TowerJazz has adopted the Calibre Auto-Waivers product to manage foundry design rule waivers associated with embedded IP. Automated waiver management significantly reduces the time and effort spent reviewing design rule violations so that designs can get to tapeout faster, while preventing accidental escapes of legitimate design rule violations that could impact yield.

To address the advancing needs of the independent engineer, Mentor Graphics has introduced three PADS tool suites. The PCB design solutions, which include the PADS Standard, the PADS Standard Plus and the PADS Professional, combine ease of use with productive design and analysis technologies.

With its Calibre xACT parasitic extraction platform, Mentor Graphics addresses a wide spectrum of analogue and digital extraction needs, including 14nm FinFET, while minimising guesswork and setup efforts for IC designers. The Calibre xACT platform combines accuracy and TurnAround Time (TAT) by automatically optimising extraction techniques for specific process nodes, applications, design sizes and extraction objectives.

Mentor Graphics has announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification. Calibre physical verification and Design For Manufacturing (DFM) platform, and the Analog FastSPICE (AFS) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models. 

In a bid to bring unity to a disparate process, Mentor Graphics has officially launched a tool that allows designers to work at the chip, package and PCB level concurrently.

A design flow solution, which automates the planning, assembly and optimisation of today’s complex multi-die packages, has been introduced by Mentor Graphics. The Xpedition Package Integrator is suitable for IC package and PCB co-design and optimisation. For true IC-to-package co-optimisation, the design flow incorporates a unique virtual die model concept.

A Signal Integrity/Power Integrity (SI/PI) product, developed for high-speed PCB designs, has been released by Mentor Graphics. The HyperLynx addresses high-speed systems design problems throughout the design flow, starting at the earliest architectural stages through to post-layout verification.