Lattice Semiconductor Corporation has announced release 1.3 of its Lattice Diamond design software, the flagship design environment for Lattice FPGA products. Users of Lattice Diamond 1.3 software will benefit from major new features, including clock jitter analysis. Lattice Diamond 1.3 software is also now integrated with Lattice’s PAC-Designer 6.1 mixed signal design tools (also announced today), providing design support for Lattice’s pro...

Lattice Semiconductor announced that its LatticeECP3 FPGA family is compliant with the PCI Express 2.0 specification at 2.5Gbps. The LatticeECP3 FPGA and its PCI Express (PCIe) IP core passed PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations at a recent PCI-SIG workshop, ensuring that Lattice’s solution is interoperable with existing PCIe 2.0 supported systems. Achieving this significant industry miles...

Lattice ECP3 FPGA: Low Power, SERDES, DDR3, Cascadable DSP, Embedded Memory Blocks-- a Perfect Balance!

Lattice Semiconductor and Flexibilis Oy today announced the immediate availability of the Flexibilis Ethernet Switch (FES) IP core. The triple speed (10Mbps/100Mbps/1Gbps) FES IP cores operate on Ethernet Layer 2 and can switch with gigabit forwarding capacity per port. Data forwarding and classification inside the switch is based on MAC address information in the packets and the prioritization scheme.

Lowest Cost, Lowest Power Programmable Gen2 SRIO Solution Available

Lattice Semiconductor and Oregano Systems - Design & Consulting Ltd. today announced the immediate availability of three comprehensive versions of the IEEE-1588 Timing Node System IP core for the LatticeECP3™ and LatticeECP2M™ FPGA families. These SoC-class versions of the IP core are characterized by different levels of functionality and performance.

Lattice Semiconductor Corporation today announced the availability of a 4 x 3.125Gbps version of the Serial RapidIO 2.1, Level 1 endpoint core utilizing the award winning LatticeECP3™ FPGA family.

Lattice Semiconductor announced the immediate availability of its new $29 MachXO2 Pico Development Kit for prototyping low power, space constrained consumer designs.

Lattice Semiconductor announced release 1.2 of its Lattice Diamond FPGA design software tool suite, the flagship design environment for Lattice FPGA products. Users of the new MachXO2 PLD devices can now generate complete systems based on the LatticeMico8 open source 8-bit controller core using the LatticeMico™ System tool, which is available with the Lattice Diamond design environment.

Lattice Semiconductor announced the immediate availability of the new LatticeECP3 Versa Development Kit, which is ideal for developing leading edge applications in a variety of markets such as industrial networking, industrial automation, computing, medical equipment, defense and consumer electronics. The low cost LatticeECP3 Versa Development Kit is now available for a promotional price of only $99.

Lattice Semiconductor announced full support for Aptina’s High-Speed Serial Pixel Interface (HiSPi) using LatticeXP2TM FPGAs. The LatticeXP2 HiSPi bridge reference design allows any Image Signal Processor (ISP) with a traditional CMOS parallel bus to interface with an Aptina HiSPi CMOS sensor.

Lattice Semiconductor announced the immediate availability of three new low-cost I/O Breakout Boards: the MachXO 2280 Breakout Board, the ispMACH® 4256ZE Breakout Board and the Power Manager II POWR1014A Breakout Board.

Lattice Semiconductor and Helion Technology today announced a portfolio of Compression and Encryption IP cores, available now, for the LatticeECP3 FPGA family. The portfolio features a Payload Compression System core that enables improved utilization of constrained channel bandwidth, making it ideal for use in Microwave Backhaul applications, Broadband Wireless Access for 802.16e (WiMAX), and, potentially, other Multi-Link Multi-In Multi-Out (MIM...

Lattice Semiconductor Corporation today announced that Thruput Ltd has chosen its LatticeXP2TM FPGAs for use in MIDAS, the first low-power, lossless real time video processing platform.

The Power Manager II family of devices integrate common, and some not-so-common, board power management functions into a single chip.

Lattice Semiconductor Corporation today announced the release of the Lattice HDR-60 Video Camera Development Kit, a production-ready High Definition (HD) video camera development system based on the LatticeECP3™ FPGA family.

Lattice Semiconductor announced the immediate availability of five new comprehensive Intellectual Property (IP) Suites to accelerate the design of electronic systems in a variety of industries using the award winning LatticeECP3 FPGA family. These five IP suites are PCI Express, Ethernet Networking, Digital Signal Processing, Video & Display, and Value.

Lattice Semiconductor will be exhibiting this year at the Embedded System Conference being held in Nuremberg. The booth number is Hall 9 Stand 180. Lattice will be featuring a number of newly introduced products along with their low cost, low power third generation ECP3 FPGAs. There will be demonstrations of these products in development environments and Lattice technical experts will be available to answer customer questions.

Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that its Platform Manager™ mixed signal device has been named Analog/Mixed-Signal IC “Product of the Year” by Electronic Products magazine, a leading trade publication for electronic design engineers

Lattice Semiconductor announced the availability of a hard copy print version of the “Power 2 You” book that provides designers with 150 pages of technical details and design considerations for implementing common circuit board power management functions. The author is Srirama (“Shyam”) Chandra, a widely published author and recognized authority on power management.