In the semiconductor industry, increase in system complexity and level of integration is driven by technology scaling. As process nodes shrink, system designers can fit more analogue and digital circuits onto the same die, to the point where the entire system is implemented within a single integrated circuit, commonly referred to as System on Chip (SoC).

HDL Design House has announced availability of its Physical Coding Sublayer (PCS) IP core (HIP 500) which enables transmission and reception of data via 8-Lanes SerDes interface. It is able to multiplex a synchronous data stream over 8 Lanes, while guaranteeing data alignment and super-frame synchronization.