Ambarella has adopted the Cadence Clarity 3D Solver for design of their next-generation AI vision processors.

Cadence Design Systems has announced that its digital full flow and custom/analogue tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies. The Cadence tool suites have achieved Design Rule Manual (DRM) and SPICE certification for TSMC’s latest N6 and N5 process technologies.

Cadence Design Systems has announced that it has broadened its long-standing collaboration with Arm to advance the development of mobile devices based on the Arm Cortex-A78 and Cortex-X1 CPUs.

Ten new Verification IP (VIP) solutions that allow engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols have been released by Cadence Design Systems.

The latest release of the Cadence digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimise power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and artificial intelligence (AI).

Optimised software for Cadence Tensilica HiFi digital signal processors (DSPs) efficiently executes TensorFlow Lite for Microcontrollers, part of the TensorFlow end-to-end open-source platform for machine learning (ML) from Google.

Cadence Design Systems has been working together with STMicroelectronics to successfully tape out a 56G very short-reach (VSR) SerDes in 7nm for a system on chip (SoC) targeted at the networking, cloud and data centre markets.

Cadence Design Systems and Broadcom have extended their collaboration to create semiconductor solutions targeting next-generation networking, broadband, enterprise storage, wireless and industrial applications. Following successful 7nm designs, the companies will now work on creating 5nm designs using Cadence digital implementation solutions.

An implementation of the Low Complexity Communications Codec (LC3) that is expected to be compliant with LE Audio, the next generation of Bluetooth audio, is available now for Cadence Tensilica HiFi DSPs and has been delivered to a lead customer.

Cadence Design Systems says that Global Unichip Corporation (GUC) successfully deployed the Cadence digital implementation and signoff flow and delivered advanced-node (N16, N12 and N7) designs for artificial intelligence (AI) and high-performance computing (HPC) applications.

Cadence Design Systems is buying RF EDA software specialist AWR from National Instruments (NI) for $160m. The acquisition is the latest building block in Cadence’s Intelligent System Design strategy which helps engineers deal with major design and implementation decisions from system to silicon.

The Cadence UltraLink D2D PHY IP from Cadence Design Systems is a high-performance, low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing and networking market segments.

A comprehensive static timing/signal integrity analysis and power integrity analysis tool, which enables engineers to create reliable designs at 7nm and below has been released by Cadence Design Systems. The Tempus Power Integrity Solution is the result of an integration between the Cadence Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution.

Cadence Design Systems was presented with four TSMC Partner of the Year awards at the TSMC 2019 Open Innovation Platform (OIP) Ecosystem Forum. Cadence achieved recognition for the joint development of the N6 design infrastructure, SoIC design solution, cloud-based productivity solution and DSP IP.

What is said to be the industry’s first Verification IP (VIP) in support of the new NVM Express 1.4 (NVMe) protocol has been released by Cadence Design Systems. The Cadence VIP for NVMe 1.4 enables designers to quickly and thoroughly verify their storage, data centre and high-performance computing (HPC) system-on-chip (SoC) designs with less effort and a greater assurance that the SoC will meet the protocol standards.

Cadence Design Systems has collaborated with Samsung Foundry and Arm to deliver a complete, high-performance digital implementation and signoff full flow for the rapid implementation of the next-generation Arm “Hercules” CPU using the Samsung Foundry 5nm Low-Power Early (5LPE) process technology.

Digital and signoff full flow and custom/analogue tools from Cadence Design Systems have achieved certification on TSMC’s N6 and N5/N5P process technologies. The Cadence tools have attained the latest N6 and N5/N5P Design Rule Manual (DRM) and SPICE certification, advancing next-generation mobile application development.

The system analysis and design market has a new solution with the introduction of the Cadence CelsiusThermal Solver, a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. Following the launch of the Clarity 3D Solver earlier this year, the Celsius Thermal Solver is the second innovative product in Cadence’s new system analysis initiative.

The Cadence analogue/mixed-signal (AMS) IC design flow has achieved certification for UMC’s 28HPC+ process technology. With this certification, mutual Cadence and UMC customers have access to a comprehensive AMS solution for designing automotive, industrial internet of things (IoT) and artificial intelligence (AI) chips using 28HPC+ technology.

Cadence Design Systems has announced that Innovium has adopted the Cadence Innovus Implementation System for its 16nm TERALYNX 12.8Tbps ethernet switches for data centres. The size and complexity of the highly innovative Innovium designs require high capacity, fast and accurate design tools for advanced-node design implementation.