Cadence has announced that Picocom has deployed the Cadence Palladium enterprise emulation platform to accelerate the verification and pre-silicon software validation of its System-on-Chip (SoC) designs for 5G open Radio Access Network (RAN) applications. Using the Palladium Emulation platform, Picocom achieved faster hardware and software integration, experiencing an emulation speedup of 1,000 times when compared with RTL simulation.

Cadence Design Systems have announced that SGS-TÜV Saar has independently certified that Cadence Tensilica Xtensa processors with FlexLock capability meet the ISO 26262:2018 standard to ASIL-D, the highest level possible under the Automotive Safety Integrity Level rating. The functional safety certification spans from base microcontroller to high-performance DSP, each with a configuration option for FlexLock to provide increased random fault...

Cadence Design Systems has announced the delivery of the Cadence Cerebrus Intelligent Chip Explorer, a new machine learning (ML)-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals.

Presto Engineering, an ASIC design and outsourced operations provider, and Cadence Design Systems have announced a collaboration to broaden semiconductor package design solutions and expertise for high-performance system-in-package (SiP) development for the automotive and Industrial IoT markets.

Cadence Design Systems has announced that Sequans Communications has successfully adopted the Cadence Virtuoso RF Solution, including the Cadence Spectre X RF Simulator and Cadence EMX Planar 3D Solver, for high-frequency RF harmonic balance and electromagnetic (EM) analysis and signoff, to develop its next-generation 5G IoT platform.

Cadence Design Systems has announced that it is expanding its collaboration with TSMC to accelerate mobile, AI and hyperscale computing application design using the integrated Cadence digital flow and custom/analogue tool suite on TSMC’s N3 and N4 process technologies.

Cadence Design Systems has announced immediate availability of Cadence IP supporting the PCI Express (PCIe) 5.0 specification on TSMC N5 process technology. The next follow-on version on TSMC N3 process technology is expected to be taped out in early 2022.

Cadence Design Systems has announced a straightforward, secure and cost-effective approach to gaining access to compute resources in the cloud when executing 3D electromagnetic (EM) simulations with Cadence Clarity 3D Solver Cloud. Clarity 3D Solver Cloud provides the ability to scale 3D finite element method (FEM) simulation capacity from 32 cores to thousands of cores using secure connections to Amazon Web Services (AWS).

Cadence Design Systems has announced that through a collaboration with Arm, customers have successfully taped out mobile SoCs using Cadence tools and the next-generation Arm mobile solution, which includes the Arm Cortex-X2, Cortex-A710, and Cortex-A510 CPUs, Mali-G710 GPU and the DynamIQ Shared Unit-110.

Cadence Design Systems has unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, and switch fabric systems on chip (SoCs).

Cadence Design Systems has announced  that JVCKENWOOD has adopted the new Spectre FX Simulator and multiple Cadence custom, analogue, digital and verification solutions to accelerate IC development of its consumer electronics applications while minimising overall design risk.

Cadence Design Systems has announced that it is expanding its collaboration with Arm to speed hyperscale computing and 5G communications SoC development using Cadence tools and the new Arm Neoverse V1 and Neoverse N2 platforms.

Cadence Design Systems has expanded its popular Tensilica Vision DSP product family with the debut of two new DSP IP cores for embedded vision and AI. Packing a 3.8 tera operations per second (TOPS), the flagship Cadence Tensilica Vision Q8 DSP delivers two times performance and memory bandwidth compared to the Tensilica Vision Q7 DSP and energy efficiency for high-end vision and imaging applications in the automotive and mobile markets.

Cadence Design Systems, has announced that the Cadence Pegasus Verification System has achieved certification for Samsung Foundry’s 5nm and 7nm process technologies. Through the collaboration with Samsung Foundry, the Cadence physical verification flow has been optimised to enable customers using Samsung Foundry’s advanced nodes to reach signoff accuracy and runtime goals in a variety of market areas, including the mobile and hypersca...

Cadence Design System has announced that it has acquired Pointwise a specialist in mesh generation for computational fluid dynamics (CFD). The addition of Pointwise’s technologies and experienced team supports the Cadence Intelligent System Design strategy and further broadens its system analysis portfolio, complementing the recently acquired NUMECA CFD technology.

Cadence Design Systems has announced that it has optimised the Cadence digital 20.1 full flow for Samsung Foundry’s advanced-process technologies down to 4nm. Through the collaboration, designers can use the Cadence tools to achieve optimal power, performance, and area (PPA) and deliver accurate, first-pass silicon for hyperscale computing applications.

Cadence Design Systems has announced that it has collaborated with GLOBALFOUNDRIES (GF) to successfully tape out a Cadence Tensilica test chip on GF’s 22FDX platform. This design used the Cadence digital full flow with Adaptive Body Bias (ABB) foundation IP along with the popular Cadence Tensilica HiFi 5 and Fusion F1 DSPs, which are suited for high-growth markets including IoT, voice processing and always-on sensor fusion.

Cadence Design Systems has announced that it has received a TSMC Open Innovation Platform (OIP) Ecosystem Forum Customers’ Choice award for a paper, ‘Optimised Digital Design, Implementation and Signoff on TSMC’s N3’, which was presented during the TSMC 2020 North America OIP Ecosystem Forum.

 Cadence Design Systems has acquired NUMECA International. The addition of NUMECA’s technologies and talent supports the Cadence Intelligent System Design strategy.

Cadence has announced the establishment of the Cadence Design Systems Professorship Fund for the Massachusetts Institute of Technology (MIT) Stephen A. Schwarzman College of Computing.