TSMC update enables development of IoT & wearable devices

Multi-year programmes to optimise performance, power and area via Cadence’s digital, mixed-signal and verification flows and complementary IP alongside ARM Cortex-A processors and ARM POP IP targeting TSMC 40nm and 28nm process technologies have been built on by the companies. The companies have also built on the the solution based around the Cortex-M processors in mixed-signal SoCs targeting TSMC 65/55nm and larger geometry nodes. The joint Cortex-M7 Reference Methodology for TSMC 40LP is the latest example of this collaboration.

“TSMC’s new ULP technology platform is an important development in addressing the IoT’s low-power requirements,” stated Nimish Modi, Senior Vice President of Marketing and Business Development, Cadence. “Cadence’s low-power expertise and leadership in mixed-signal design and verification form the most complete solution for implementing IoT applications. These flows, optimised for ARM’s Cortex-M processors including the new Cortex-M7, will enable designers to develop and deliver new and creative IoT applications that take maximum advantage of ULP technologies.”

“The reduction in leakage of TSMC’s new ULP technology platform combined with the proven power-efficiency of Cortex-M processors will enable a vast range of devices to operate in ultra energy-constrained environments,” said Richard York, Vice President of Embedded Segment Marketing, ARM. “Our collaboration with Cadence enables designers to continue developing the most innovative IoT devices in the market.”