Silicon Labs Eliminates Jitter With Industry's Easiest-To-Use Clock Cleaner IC

As networking and telecom hardware designs migrate to higher speeds and greater complexity, timing architecture has become a key consideration in the overall system design. Managing clock jitter is especially critical in high-speed applications since this noise degrades overall system performance, impacting the design's bit-error-rate (BER) and signal-to-noise ratio (SNR). The Si5317 clock cleaner provides a simple, flexible and cost-effective jitter filtering solution for these performance-sensitive applications.

The Si5317 effectively removes unwanted noise on any clock frequency from 1 to 710 MHz and produces two ultra-low jitter output clocks at the same frequency as the input. Unlike traditional clock ICs or discrete phase-locked loop (PLL) module solutions requiring multiple components to support different frequencies, one Si5317-based design and layout supports jitter attenuation for any <710 MHz clock signal, enabling design reuse across multiple applications. Designers can use simple pin settings to configure the frequency range and PLL bandwidth, eliminating the need for firmware and serial programming required by traditional clock IC solutions.

The Si5317 is the industry's most versatile and user-friendly jitter attenuating clock cleaner, providing an ultra-low jitter solution for high-performance and cost-sensitive access and networking applications that require exceptionally clean clocks, said Mike Petrowski, general manager of Silicon Labs' timing products. The Si5317 simply drops into the clock path to provide jitter attenuation on clock signals up to 710 MHz without requiring firmware configuration or BOM modifications to accommodate different frequencies.

Based on Silicon Labs' patented DSPLL® architecture, the Si5317 clock cleaner delivers best-in-class jitter performance (0.29 ps RMS), improving BER and SNR in jitter-sensitive applications. This exceptional jitter performance - typically one-third lower jitter than competing clock ICs with integrated oscillators - enables a significant portion of the system jitter budget to be allocated to other devices, simplifying component selection and clock tree design.

The Si5317 integrates a single supply voltage regulator with excellent power supply noise rejection. This streamlined power supply design eliminates the need for multiple supply rails and discrete ferrite beads. On-chip power regulation also minimizes the board design's sensitivity to high-speed noise and switching power supplies, reducing the risk that the power supply noise might impact the design's overall jitter performance.

As the industry's most highly integrated jitter cleaning clock, the Si5317 requires no external PLL components, simplifying PCB design and layout in space-constrained applications while minimizing the threat of board-level noise impacting jitter performance. On-chip DSPLL technology eliminates the need for a charge pump and/or loop filter design required by traditional VCXO-based PLL modules and clock ICs. This high level of integration minimizes design time and development risk by guaranteeing loop stability and jitter performance across temperature, process and voltage variation. Combining all PLL components into a single device also eliminates sensitive noise entry points between discrete PLL components, improving immunity to board-level noise.

In addition to jitter attenuating clocks, Silicon Labs' broad portfolio of mixed-signal timing ICs includes programmable XO/VCXOs, CMOS-based silicon oscillators, high-performance clock generators, low jitter clock multipliers, buffers and physical layer timing devices. The Si5317 clock cleaner can be combined with many of these timing devices to enable a complete, ultra-low jitter timing solution. Companion timing IC products for the Si5317 include the Si500 silicon oscillator, the Si5338/34 <710 MHz differential clock generators, the Si5355/56 <200 MHz CMOS clock generators and the Si5330 low jitter clock buffers. The Si5317 easily connects to any of these timing ICs to provide two ultra-low jitter output clocks.