Lattice and Flexibilis announce first FPGA ethernet switch IP cores with HSR (IEC 62439-3) protocol support

Quality of service is supported with up to four queues per port. This Ethernet switch IP core is available in five versions that vary in their number of ports and functionality:
High Availability Seamless Redundancy QuadBox FES
High Availability Seamless Redundancy RedBox FES
8-port FES
4-port FES
3-port FES

The FES with HSR IP cores enables designers of substation automation and industrial networking applications to immediately and confidently apply the emerging High Availability Seamless Redundancy (HSR) protocol using LatticeECP3™ FPGAs. This IEC protocol (IEC62439-3) provides cost effective redundancy with no single point of failure and zero recovery time in case of failure. It is applicable across a range of applications that demand high availability and sub-microsecond accuracy. Target applications include smart grid substation automation and networked industrial automation gear, as well as in high availability network equipment.

The FES IP cores are equipped with IEEE 1588 version 2 end-to-end transparent switch functionality, which significantly improves the ability to resist the degradation of clock information quality in larger networks. This ability is critical in meeting the strict quality of service (QoS) requirements in wireless backhaul, wireline access, datacenter bridging and industrial Ethernet application. This feature makes the FES IP cores suitable for applications such as microwave backhaul routers, cell side routers and industrial automation products.

“We are pleased to provide our Flexibilis Ethernet Switch IP to Lattice’s OEM customers,” said Tomi Norolampi, GM of Flexibilis Oy. “We were able to use our expertise with communications and industrial network equipment to provide advanced functionality in a compact implementation. The LatticeECP3 FPGA provided us the perfect platform to deliver the most value through our IP.”

“Our collaboration with Flexibilis provides our customers with access to a complete system solution, including development boards, enabling them to rapidly deploy compliant Ethernet technology for low cost to high performance applications using LatticeECP3 FPGAs,” said Lalit Merani, Senior Manager of Product Marketing at Lattice Semiconductor. “These system IP cores enable our OEM customers to immediately implement the IEC High Availability Seamless Redundancy draft standard in their designs today, and upgrade their installed base as the standard evolves.”

About the Lattice ECP3 FPGA Family
The LatticeECP3 FPGA family is comprised of the lowest power, SERDES-enabled FPGAs in the market today. The family’s five FPGAs offer standards-compliant, multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature fast LVDS I/O as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive video camera and display, wireline, and wireless infrastructure applications.