Instruction set architecture to become standard open architecture

The 'Hands-On RISC-V Tutorial Session' will take place 13^th July from 1-6pm. EDT, following the RISC-V Workshop at MIT in Cambridge, Massachusetts.

RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, and is now set to become a standard open architecture under the governance of the RISC-V Foundation. The combination of Microsemi’s SmartFusion2 and Libero SoC create an ideal ecosystem to target a RISC-V core for many embedded applications in the industrial segment. The low power and security of SmartFusion2 is a sound architecture for customers seeking to protect their intellectual property (IP) and ensure long-term support for their design. The Libero SoC Design Suite allows designers to implement their design and efficiently pack the FPGA logic elements (LEs), yielding a cost-effective solution.

“We are pleased to be a part of RISC-V’s event, as it presents an ideal opportunity for attendees to see firsthand how embedding RISC-V into our award-winning SmartFusion2 SoC FPGAs can optimise design performance and accelerate development time,” said Ted Marena, Director of SoC FPGA marketing at Microsemi. “Arrow’s SF2+ development board is a full-feature hardware development kit that enables software and hardware engineers to reduce not only the area of their board, but also the cost and complexity of working with multiple sensors and interfaces.”

RISC-V is designed to be scalable for a wide variety of applications, easy to implement with regard to size and power, and offered under a permissive Berkeley Software Distribution (BSD) open source license. The Arrow Microsemi SmartFusion2+ Evaluation board contains memory for RISC-V code execution and storage. In addition, there is a system-on-module that allows customers to use a choice of SmartFusion2 densities, anywhere from 10k LEs to 90k LEs. These features make the Microsemi platform ideal for the development of RISC-V based designs.

Microsemi’s hands-on RISC-V training, which has a fee of $25 and is comprised of four 60-minute tutorials with Q-and-A sessions, has been specially developed to run on Arrow’s Microsemi SmartFusion2 evaluation board. All registered attendees will receive a complimentary evaluation board, supplied jointly by Arrow and Microsemi, to continue their design efforts following the event.

The four tutorials will showcase Microsemi’s leadership role in the emerging RISC-V ecosystem with participation from SiFive, Technolution and VectorBlox. Topics include:

• 1 p.m.: “Arrow Microsemi SmartFusion2+ Evaluation Board Bring-Up”
• 2:10 p.m.: “VectorBlox ORCA RISC-V Processor with Vector Extensions”
• 3:40 p.m.: “How RISC-V Can Make Your Products Safer and More Secure”
• 4:50 p.m.: “RISC-V in Chisel on FPGA”

The “Arrow Microsemi SmartFusion2+ Evaluation Board Bring-Up” session is a simple tutorial to help users bring up the evaluation board and associated tools using the supplied VirtualBox VM. This capability will be required when participating in tutorials 2, 3 and 4. Those tutorials will use Microsemi’s Libero SoC Design Suite, which provides high productivity with its comprehensive, easy to learn, easy to adopt development tools for designing with Microsemi’s power-efficient flash FPGAs, SoC FPGAs and radiation-tolerant (RT) FPGAs. The suite integrates industry standard Synopsys SynplifyPro synthesis and Mentor Graphics ModelSim simulation with best-in-class constraints management, debug capabilities and secure production programming support.

For more information on the series of tutorials, visit here. Register here.