Boundary Scan Platform SCANFLEX accesses new Debug Interfaces for Processor Emulation Test

“Our new TIC hardware enables a completely new quality in the fusion of Boundary Scan and processor emulation. Now we can support virtually each kind of target and application using the same interface“, says Thomas Wenzel, co-founder of GOEPEL electronic and managing director of the JTAG/Boundary Scan Division. That means, we are the first vendor of such a universal solution and smooth the way for enhanced applications in processor assisted test and programming strategies at both board and system level. Additionally, in this innovation our awarded SCANFLEX® solution proves its future oriented architecture.”

TIC020 has specifically been developed for the combined utilisation with the adaptive streaming technology VarioTAP®, and in addition to common bus signals comprises of a number of further emulation signals that can flexibly be integrated into a streaming procedure. That brings TIC020 into the position to cover various protocols and target interfaces, among them the standards IEEE1149.1, IEEE1149.6, IEEE1149.7, IEEE1532 and IEEE-ISTO 5001, as well as plenty of non JTAG interfaces such as BDM (Background Debug Mode) from Freescale®, DAP (Device Access Port) from Infineon®, SBW (Spy-Bi-Wire) from Texas Instruments®, SWD (Serial Wire Debug) from ARM® and many more.
Because SCANFLEX® – in contrast to other systems – is based on a real parallel TAP architecture and doesn’t internally cascades the scan chains, applications with several different non JTAG targets can be implemented by utilising multiple TIC020 modules. For instance, the TAP Transceiver SFX-TAP8 supports up to eight independent interfaces, which can be controlled either separately or full synchronously for Gang applications.

The new solution has user benefits in the lab as well production. Prototypes can be tested and validated even faster per MCU without the necessary firmware. At the same time, dynamic fault coverage and test depth in general are increased in the production process. Furthermore, all test and programming procedures can be executed on the same platform and without utilising processor specific Pods, which results in an easier handling, cost reduction and increase in process effectivity.

The new TIC module series member has a compliant form factor with all existing first generation TAP Interface Cards, whereby applied SCANFLEX® TAP Transceivers can be easily upgraded by the user whilst protecting current investments. The electric characteristics such as flexible programmability of I/O signals and compensation of dynamic run time delay are also compliant. TIC020 is fully supported in the industry leading JTAG/Boundary Scan software SYSTEM CASCON™, which automatically recognizes the module via the AutoDetect feature.

Product shipping release is scheduled for fourth quarter of 2010.