Imperas announce participation at DAC 60

The RISC-V instruction set architecture (ISA) open standard has accelerating momentum in the semiconductor community. This is due to the open nature of the ISA, enabling users to build domain-specific processors that can help to differentiate products. Is this momentum built on real SoCs going to production? What is needed to develop a RISC-V based SoC? How mature is the specification? Is RISC-V ready for prime time? Who takes responsibility for verification?

This panel, from various areas in the RISC-V community/ecosystem from fab through to end user, will try to address these questions and more, and provide perspectives on the readiness of RISC-V, and the path to RISC-V based silicon.

Organiser: Larry Lapides, Imperas Software

Moderator: Calista Redmond, RISC-V International

Panel: Bob Brennan, Intel Foundry Services

            Rick O'Connor, OpenHW Group

            Simon Davidmann, Imperas

            Balaji Baktha, Ventana Micro

            Himanshu Sanghavi, Meta

When: Wednesday, July 12, 10:30am (PDT)

Where: 2012, 2nd Floor

"'RISC-V is inevitable' has been the tagline for RISC-V International this year," said Simon Davidmann, CEO at Imperas Software Ltd. "But when is it coming? Is RISC-V here, now?  (Our customers seem to think so!)  We've organised this panel to provide different perspectives on the maturity of the complete RISC-V ecosystem, from varying community members. It's exciting that these key participants will be answering questions; come prepared with your questions!"

Presentation: extending RISC-V with custom instructions

One of the attractive features of RISC-V is the ability to add, while maintaining ecosystem software support, new optimised instructions and extensions to a processor implementation. At first it appears as simple task to look at opportunities in the application code that could be accelerated with some dedicated new hardware. However, since hardware typically has a much longer life cycle than software, future updates and roadmap needs must be anticipated. Thus, the art of ISA design is using fine-grain analysis to accelerate just the key steps while leaving sufficient flexibility to support new software updates and advances. Also, in multi-core arrays the use of custom extension can offer a lightweight communication channel between processor elements (PE). This extends the scope beyond the processor itself into system design and analysis.

This talk will illustrate the key profiling and analysis steps for custom extensions and optimisation, and outline the requirements for verification. After completing the design and verification phases, the final step is to support software developers in the adoption of the new extensions as part of the go-to-market solution.

Author: Jon Taylor, Imperas Software

When: Monday, July 10, 12:40pm (PDT)

Where: RISC-V Zone Theater

Presentation: open standards and methodologies for RISC-V verification testbenches

With the growth in the adoption of RISC-V optimised implementations, SoC design verification teams are now facing the challenges of processor verification. Traditional SoC methods for block-level testing do not scale to match the complexity of a multi-state processor implementation. This talk outlines the new methodologies and resources available to DV teams for RISC-V verification.

At the centre of any verification plan is a quality test bench, that accommodates all the design functionality with analysis features, which has a direct correlation to the quality of the final RTL. This talk outlines the RVVI (RISC-V Verification Interface) an open standard for the key infrastructure of quality test benches. RVVI also covers the methodologies and guidelines to address all levels of RISC-V implementation including the latest extensions for vectors, crypto, PMP, and privilege modes, plus custom instructions. Based on the RVVI standard many additional DV resources are freely available with test suites and functional coverage libraries for many of the ratified extensions.

This talk includes examples from some popular open-source cores to illustrate the flexibility of RVVI plus insights into using a standards-based approach with SystemVerilog and UVM.

Presenters: Aimee Sutton, Imperas Software

                    Lee Moore, Imperas Software

                    Simon Davidmann, Imperas Software

When: Monday, July 10, 2:45pm (PDT)

Where: 2012, 2nd Floor

Presentation: RISC-V verification - introduction to the lost art of processor verification

The open standard RISC-V Instruction Set Architecture (ISA) offers developers new design freedoms for an optimised processor while maintaining all the benefits and advantages of full ecosystem support. RISC-V verification requires both functional tests and compliance with the ISA specification. Now all adopters that choose to explore the new design freedoms of RISC-V will also need to consider the challenge of RISC-V verification.

This talk highlights the open standards such as the RISC-V Verification Interface (RVVI) for test bench infrastructure that is supported with both commercial and freely available resources with test suites, coverage libraries, and other Verification IP.

This talk will also review the latest RISC-V verification approaches, including the complexities of vector extensions, PMP, crypto, privilege, and custom instructions with the 'lock-step-compare' methodology that supports asynchronous events and debug operations.

Author: Aimee Sutton, Imperas Software

When: Tuesday, July 11, 12:40pm (PDT)

Where: RISC-V Zone Theater

For those planning to visit DAC 2023 and are interested in getting to know Imperas Software experts, visit Imperas at Booth 2336