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ROHM Semiconductor to Announce High Density and High Speed EEPROM Series

18th October 2012

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Datasheet

ROHM Semiconductor introduces its new high density and high speed EEPROM series. The line-up of this new member of BR24 family with I2C Bus is adding the high densities 512k and 1Mbit, which were not available previously. In addition it will also offer alternatives for the existing parts from 1k to 256kbit, but with the possibility to increase the speed to up to 1Mhz. All EEPROMs feature a double cell structure to eliminate accidental failures, and a double protection circuit to prevent writing errors. This makes them ideal memory solutions for a wide range of devices such as consumer, industrial and automotive applications.

Rewriting is performed by passing electrons through a tunnel oxide film. This, however, causes deterioration of the film, eventually leading to memory failure where the memory cell data is locked at ‘1’ and cannot be rewritten to. ROHM’s double cell structure prevents this by allotting two cells for each memory bit, connected in an OR configuration so that the second cell is able to operate upon failure of the first.

All LSIs become unstable during power ON and OFF: EEPROMs are even more susceptible to failure, making it impossible to even recover from one malfunction. In response to this, ROHM integrated a double protection circuit consisting of a Power ON Reset (POR) block that resets during start-up and a Low Voltage Write Error Protection Circuit (LVCC) that prevents write operations and resets during low voltage conditions (LVCC and below).

Data can be rewritten up to 1.000.000 times and stored for 40 years. Providing a wide range of memory capacities, from 32k up to 1Mbit, the new devices can be delivered in standard packages such as SO8 and TSSOP8. All control functions are available through two ports of the serial clock (SCL) and serial data (SDA). Facilitating the design, microcontroller port can be saved by connecting other devices but EEPROMs to the same port and an integrated filter is built in the SCL/SDA terminal in order to eliminate noise.

Key features:

* I2C Interface with up to 1MHz frequency
* High reliable double cell structure
* Double reset method for twice the safety
* Wide range of memory capacities: 32k to 1Mbit (1k to 16kbit will follow later)
* Worldwide standard packages (JEDEC): SO8, TSSOP8 and others
* 1.7V to 5.5V supply voltage range
* Page write mode useful for initial value write at factory shipment
* Auto erase and auto end function at data rewrite
* Low current consumption
* Data rewrite up to 1.000.000 times
* Data retention time of 40 years
* Integrated noise filter for the data lines

Availability
Densities from 32k to 256kbit are already in mass production. 1Mbit parts are available as samples from now on, 512kbit parts from middle of October onwards.