Cadence collaborates with Arm to jumpstart the automotive chiplet ecosystem

This collaboration introduces a chiplet-based reference design and a software development platform specifically designed to enhance advanced driver assistance system (ADAS) applications. It features a scalable chiplet architecture and ensures interface interoperability, promoting industry-wide collaboration, facilitating heterogeneous integration, and encouraging system innovation.

Constructed with the latest generation of Arm Automotive Enhanced technologies and Cadence IP, this solution also includes a software stack development platform acting as a digital twin. This setup is compliant with the Scalable Open Architecture for Embedded Edge (SOAFEE) initiative software standard, which supports software development ahead of hardware availability and aids in system integration validation. This approach is geared towards speeding up both hardware and software development processes, thus accelerating the product's time-to-market.

As ADAS and SDVs become more prevalent, there's an increasing demand for complex AI and software capabilities, along with a need for higher interoperability and collaboration within the automotive electronics ecosystem. Chiplets emerge as a promising solution for rapidly customising 3D-IC systems for various automotive applications, contingent on seamless operation among chiplets from different IP providers. Additionally, the swift evolution of automotive technology necessitates a software development platform that allows developers to start early in the design process while IP and chiplets are still under development.

This innovative solution architecture and reference design set a new standard for chiplet interface interoperability, addressing a significant industry challenge. The Cadence components of the solution encompass:

• Helium Virtual and Hybrid Studio for the creation of virtual and hybrid platforms and Helium Software Digital Twin for scalable software developer deployment
• I/O IP solutions supporting key interface and memory protocols, including Universal Chiplet Interconnect Express (UCIe) for chiplet-to-chiplet communication
• A comprehensive compute IP portfolio, featuring the advanced AI Neo™ neural processing unit (NPU) IP, the NeuroWeave software development kit (SDK) for ML solutions, and top-tier DSP compute solutions

Dipti Vachani, Senior Vice President and General Manager at Arm's Automotive Line of Business, emphasised the dynamic nature of the automotive industry: “The automotive industry is evolving rapidly and AI and software advancements are emphasising a greater need to speed up development cycles. Together with critical ecosystem partners like Cadence, we’re enabling faster software and hardware development by bringing together a complete solution of design and verification technologies underpinned by the latest Automotive Enhanced technologies from Arm, allowing developers to start building for next-generation SDVs well before silicon is available in the market.”

Paul Cunningham, Senior Vice President, and General Manager of the System Verification Group at Cadence, highlighted the importance of virtual platforms and chiplets in the development process: “Reducing the overall system design workload and shifting hardware and software development left are both crucial to meet shrinking time-to-market windows when developing today’s increasingly complex SDVs. Virtual platforms and chiplets are both key enablers for automotive 3D-IC SoC developers. Working closely with Arm, we are addressing key inefficiencies in both software and hardware development and verification processes, while catalysing the multi-die chiplet ecosystem for automotive semiconductors.”

The virtual platform and component IP for the reference design are currently available for early adopters, marking a significant step towards innovative automotive development.