Xilinx FPGAs Contribute to Global Standardization of Cryptographic Module Security Evaluation

The SASEBO-GII board uses Virtex-5 FPGAs, which has about four to seven times larger logic area than the Virtex-II FPGA used in the SASEBO-G generation, and therefore enables the evaluation of complex circuits that could not be implemented previously. Greater integration has allowed AIST to reduce board surface area to a third of its former size and enabled considerable miniaturization. The Virtex-5 device's partial reconfiguration capabilities will enable the research and development of highly-advanced hardware security systems. The SASEBO-GII board is expected to serve as the standard for carrying out cryptographic hardware experiments and for international programs involving hardware security evaluation.

With advances in digital information devices and the spread of broadband networks, cryptographic algorithms are being widely used to prevent the leakage or falsification of data. However, improper implementation of the algorithms can expose entire security systems to the risk of attacks. The ISO/IEC 19790 and 24759 standards and the FIPS 140-2 standard issued by the U.S. National Institute of Standards and Technology (NIST) were established as a means for third party testing and validation of cryptographic modules. Japan's Information-Technology Promotion Agency (IPA) also operates a Japan Cryptographic Module Validation Program (JCMVP) that conforms to these standards.

These standards do not, however, address side channel attacks, which are a new form of attack that exploit confidential information derived from cryptographic module timing information, power consumption, electromagnetic leaks and other sources. NIST is currently developing FIPS 140-3 as a standard that addresses such attacks, and the ISO/IEC standard is also expected to be revised. SASEBO-GII is the latest version of the FPGA board that AIST has been researching and developing since fiscal 2006 as a standard testing platform for working out the standards.

The SASEBO-GII board is the third generation of SASEBO boards to use Xilinx FPGAs. In the new board, Virtex-5 LX30 and LX50 FPGAs are mounted for the main cryptographic circuit and a Spartan-3A FPGA for the interface circuit to enable various partial reconfiguration as well as side channel attack evaluation experiments. Equipped with multiple power monitoring points, the Virtex-5 FPGAs on the board are capable of including embedded processors, an SRAM for data storage, driving user LEDs and I/Os, while also providing the flexibility for users to implement their own interfaces. The FPGAs also provide extended inputs for controlling power and clock speeds to conduct advanced physical attack evaluation experiments.

SPI-ROM and Slave-SelectMap are available as configuration methods to enable the evaluation of dynamic and static partial reconfiguration systems through control schemes targeting the Spartan-3A device. Configuration via a USB cable is also supported, which means various experiments can be conducted on the SASEBO-GII board only with one USB cable connected to a PC workstation.

Cryptographic technology is an important element that makes up the technological foundation for today's ubiquitous network, said Xilinx Vice President, Japan Sales, Sam Rogan. We're privileged that Xilinx FPGAs are making a contribution to international cryptographic module evaluation programs as a result of their adoption by AIST for the new SASEBO-GII boards.

Tokyo Electron Device Ltd., Xilinx K.K.'s sales representative, will commercialize the SASEBO-GII boards and is now taking advance orders. Xilinx will demonstrate the SASEBO-GII board's capabilities at its booth (E-18) during Embedded Technology 2009, opening at Pacifico Yokohama on Wednesday, Nov. 18. Also, Researcher and Assistant Professor, Ph. D. Yohei Hori of Chuo University, who is a member of SASEBO-GII development team, will give a lecture about a partial reconfiguration during the FPGA track at the conference.