X-FAB Qualifies Cadence Physical Verification System for All Process Nodes

“Creating an advanced mixed-signal SoC presents significant challenges,” said Dr. Jens Kosch, chief technology officer at X-FAB. “Our customers welcome any opportunity to streamline the development process, so we were pleased to qualify and endorse the Cadence Physical Verification System for our process technologies at X-FAB.”

The Cadence Physical Verification System delivers in-design and final signoff design rule checking (DRC) and layout versus schematic (LVS) verification at transistor, cell, block, and full-chip/SoC levels. It integrates with industry-standard end-to-end digital and custom/analog flows, enabling more efficient Silicon Realization methodologies.

“Design teams prefer to stay within the same environment for design, implementation, and verification to shorten turnaround time and ensure design quality. This qualification means X-FAB customers can confidently conduct all required physical verification using the Cadence Physical Verification System, remaining in the design and implementation cockpit to improve productivity,” said John Murphy, group director, alliances marketing at Cadence. “We worked closely with X-FAB to address all its stringent verification qualification requirements, meeting and exceeding all signoff parameters. This type of deep collaboration with leading foundries is an essential element of the EDA360 vision.”

By tightly integrating design rule checking into the Cadence implementation technologies, design teams will be able to validate against signoff DRC validation as they edit, allowing them to find and fix errors earlier in their flow while saving them time in longer loops through standalone signoff solutions. The result is faster time to tapeout. Cadence and X-FAB continue to work closely together to provide validated signoff verification decks for their mixed-signal customers.