Toshiba supports DATE with ‘fabless’ expert panel

Entitled ‘Supporting fabless semiconductor design at 65nm and beyond’, the TEE ASIC & Foundry panel session will be held on Wednesday 22nd April from 16:15 to 17:00 in the DATE exhibition theatre. The session will bring together representatives from a number of leading fabless manufacturers who will look at the process technologies available to chip designers targeting multimedia and communications applications. Differences between a traditional foundry model and an ASIC-orientated approach will also be considered. Among the topics that are likely to be debated are critical issues for future designs including technology cost, skills, risk of failure and system flow requirements in areas such as EDA, IP and external design support.

Panel members will be Rainer Kaese, the senior manager for SoC business development at Toshiba Electronics Europe; Jose Calero, CTO of DS2, a designer of powerline communication ICs; and Fernando Barbero, director of SoC development for TV module specialist SIDSA.

Pre-arranged meetings with Toshiba’s ASIC & Foundry specialists will be held in meeting room Risso 7A. Here visitors will be able to discuss specific project requirements and find out more about Toshiba’s advanced process technologies, business model and local support services. To see the TEE official DATE ‘09 invitation, and to find out more about the ASIC & Foundry business, visit www.toshiba-components.com/ASIC. To arrange a meeting with ASIC & Foundry specialists during the exhibition e-mail date2009@tee.toshiba.de.

Toshiba’s corporate R&D team will present a paper on ‘Design and implementation of scalable transparent threads for multi-core media processors’ at 17:00 on Wednesday 22nd April (http://www.date-conference.com/conference/date09-session-8-8 ) . On Thursday 23rd April At 17:15 Toshiba Research Europe’s Telecommunications Research Laboratory will present a paper entitled ‘Implementation of a reduced lattice MIMO detector for OFDM systems’ (http://www.date-conference.com/conference/date09-session-12-3). Finally, on Friday 24th April, Toshiba Corporation will look at ‘Hierarchical cache system for 3D-multi-core processors in sub 90nm CMOS’ as part of that day’s workshop on W5 3D Integration (http://www.date-conference.com/conference/date09-workshop-W5).

The TEE ASIC & Foundry Business Unit’s open and advanced Integrated Device Manufacturer (IDM) model allows customers to speed development and reduce risk by choosing a single partner for design, implementation, production and full-service supply chain management. The company offers a wide range of leading edge CMOS solutions based on Toshiba’s own process developments. Customised SoC development is supported through a broad lineup of Intellectual Property (IP), including in-house and third party analogue and digital IP, ARM and MIPS processors, and embedded memory options.

To speed application development Toshiba offers local competence and support through its European LSI Design and Engineering Centre (ELDEC). ELDEC’s highly skilled engineers have many years of experience in EDA, analogue development and design, implementation and layout. In addition, short development Turn-Around-Time (TAT) and low risk is assured thanks to flexible SoC design methodologies, optimised factory processes and professional project management.