Analysis

Toshiba support for GSA & IET International Semiconductor Forum includes keynote address and access to ASIC and Foundry specialists

27th April 2009
ES Admin
0
Toshiba Electronics Europe has announced its active support for the GSA & IET International Semiconductor Forum on 2nd and 3rd June 2009. The TEE ASIC and Foundry business unit will be exhibiting at the forum as well as offering private meetings with its team of specialists. Mr Noguchi, Technology Executive with the System LSI Division of Toshiba Semiconductor Company, will present a keynote address during the Forum’s conference sessions.
Visitors to the Toshiba booth will be able to find out more about the processes, methodologies and support that the TEE ASIC & Foundry business unit can provide for companies looking to develop advanced system-on-chip (SoC) technologies. The company is also offering visitors the opportunity to pre-arrange one-on-one meetings with ASIC & Foundry specialists in a private conference room. Mr Noguchi’s keynote address - ‘Are ASIC's Really on the Decline? The ASIC Model: Future Directions’ - will take place on 3rd June at 11.15am.

To see the TEE official GSA & IET International Semiconductor Forum invitation, and to find out more about the ASIC & Foundry business, visit www.toshiba-components.com/ASIC. To register interest in arranging a private a meeting with ASIC & Foundry specialists during the exhibition e-mail GSA2009@tee.toshiba.de.

The TEE ASIC & Foundry Business Unit’s open and advanced Integrated Device Manufacturer (IDM) model allows customers to speed development and reduce risk by choosing a single partner for design, implementation, production and full-service supply chain management. The company offers a wide range of leading edge CMOS solutions – including 65nm and 40nm processes and 130/65nm RFCMOS technologies - based on Toshiba’s own process developments. Customised SoC development is supported through a broad lineup of production-ready, silicon-proven mixed-signal Intellectual Property (IP), including in-house and third party options.

To speed and simplify the implementation of SoCs based on the company’s advanced CMOS processes, Toshiba offers a variety of development handover models in addition to full ASIC development. Hybrid models allow customers to develop mixed-signal IP development and use Toshiba’s chip-level integration, while COT (customer own tooling) models allow for physical data handover (GDSII) by the customer.

In each handover model, engineers at Toshiba’s local European Design and Engineering Center (ELDEC) can provide local competence and support. ELDEC engineers have many years of experience in EDA, analogue development and design, implementation and layout. In addition, short development Turn-Around-Time (TAT) and low risk is assured thanks to flexible SoC design methodologies, optimised factory processes and professional project management.

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