Toshiba's New Platform Technology for 40nm CMOS Process

9th January 2009

Toshiba

ES Admin

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Toshiba has announced a 40nm CMOS platform technology based on 45nm process technology co-developed with NEC Electronics. The new platform fabricates SOC for power-critical mobile applications that consume less than half the power of 65nm generation LSI. The company also announced that it expects to deploy the technology on samples in the fourth quarter of FY2008, and in mass production in the second quarter, FY2009.

Advanced mobile application requires reduced chip size and lower power consumption. Process migration is a solution to meet the demand, however, shorter channel length tends to cause current leakage. Both reduction of power consumption and chip size shrinkage require controlling channel impurity concentration and fining layout.

Toshiba has established and applied new platform technology for a new activation sequence using flash lamp anneal, optimizing impurities in the ion implantation process, and applying Hafnium incorporated insulators and DFM (design for manufacturing) technologies. Doubling the flash lamp anneal process boosted both the PMOS and NMOS performance. Doping germanium with nitrogen in the ion implantation process minimized concentration in the channel area, which contributes to higher transistor performance. Hafnium incorporated insulators improve drive current by increasing threshold voltage without excess concentration of channel impurities. Application of DFM technologies enabled aggressively scaled layout with lower lithographic defects.

Toshiba will further enhance development of low-power-consumption technology for advanced generations.