Toshiba Develops High Performance CMOS Device Technology for 20nm Generation LSI

Toshiba has announced that it has developed a breakthrough technology for steep channel impurity distribution that delivers a solution to a key problem for 20nm generation CMOS technology. The technology opens the door to a future generation of LSI fabricated with bulk CMOS technology, the mainstream technology in today's LSI, by achieving the world's first practical fabrication process applicable to 20nm generation CMOS devices.

Toshiba unveiled the new technology at the 2009 International Electron Devices Meeting (IEDM) held in Baltimore, Maryland, U.S.A. from December 7 to December 9, one of the semiconductor industry's leading international conferences.

The new technology forms three layers on the surface of the channel: epitaxial silicon (Si), carbon-doped silicon (Si:C), and boron-doped Si:C. The top epitaxial Si layer functions as a low resistance path for the electrons and the holes; the intermediate Si:C acts as a defensive layer to prevent impurity diffusion; and the bottom boron-doped Si:C layer suppresses the fixed charge caused by the Si:C layer formation. Toshiba has confirmed that application of this novel structure achieves a boost in performance surpassing that of the conventional channel structure by 15 to 18%. This structure can be applied to both the nMOS and pMOS transistors to configure CMOS devices, with a simple process that adds a few layer-forming steps.

Previous R&D efforts have largely focused on nMOS transistors, in which channel impurities diffuse easily, or on examining the introduction of new solutions, such as SOI wafers and a 3D gate structure. Toshiba's new technology realizes a high-performance 20nm generation process without employing such new solutions, simply by optimizing impurity materials, device structures and processes.