The MEDEA+ FOREMOST Advanced Technology R&D Project: Short-listed for 2010 EUREKA Innovation Award

The EUREKA German Chairmanship invited one member from each of the three short-listed projects at the EUREKA stand at the Hannover Messe (April 19-20,) in Germany. The three finalists will also be invited to the award ceremony itself, which will take place in Berlin on Thursday 24 June 2010. The overall winner of the award will be announced at this ceremony, attended by numerous European dignitaries, including ministers and ambassadors.

The MEDEA+2T103 FOREMOST project, which was successfully completed in mid-2009, was launched in January 2006 with the goal of maintaining Europe’s strength in CMOS integrated circuit technology and manufacturing, through the development, integration, and demonstration of advanced process modules and transistor architectures for full 45nm node technology in industrial 300 mm wafer fabrication plants. It was notably supported by the national authorities of France, Germany and the Netherlands, among others, working together within the frame of the EUREKA MEDEA+ program.

The project targeted both CMOS logic and DRAM/FLASH memory process technologies, with the aim of promoting synergy between the competences of leading European semiconductor manufacturers (including STMicroelectronics, NXP, Freescale, Qimonda), as well as essential material and equipment suppliers (Air Liquide, Aixtron, ASM ) and world-class institutes and laboratories. (See note (1) for the complete list of FOREMOST consortium members).

The project achieved all of its main goals and it paved the way for new challenging system-on-chip developments. In addition, project partners published more than 80 papers, filed 30 new patent applications, and gave presentations at more than 40 conferences. The impact of successful R&D projects such as FOREMOST can be measured through subsequent achievements in major fields of application that boost the position of Europe’s chipmakers such as STMicroelectronics and their equipment and materials suppliers in the world market.

For example, in the mobile communications field, ST-Ericsson, a global leader in mobile platforms and semiconductors, demonstrated a dual-core smartphone platform, with each core running at a clock speed of 1.2 GHz, at the Mobile World Congress in February 2010. The performance breakthrough, which set a new benchmark for an integrated smartphone platform on a multicore system, will enable handsets to run several graphically-rich applications simultaneously, integrating HD or 3D video and social networking with online map-navigation and augmented reality. It will also dramatically enhance the responsiveness and experience of the smartphone user interface. The U8500 was designed on STMicroelectronics’ leading-edge low-power 45nm process, which is a key enabler to achieve the performance demonstrated at the Congress.

Similarly, in the Home Entertainment and Displays field, STMicroelectronics demonstrated the potential of the STi7108 at the January 2010 Consumer Electronics Show (CES) in Las Vegas. The STi7108 is the first in ST’s third generation of high-definition chips uses unprecedented CPU performance to provide the end user with an exciting 3D HDTV user experience. It also delivers market-leading energy efficiency, using its low-power, configurable architecture and ST’s low-power manufacturing process.

“This EUREKA Innovation Award recognizes the collective effort of European organizations, from leading chip manufacturers, equipment and material suppliers including SMEs (Small and Medium Enterprise's) to industry-oriented research institutions and universities, partnering to develop advanced knowledge that will enable the European chip industry to maintain its strong presence in the worldwide microelectronics landscape,” said Dr. Dominique Thomas, STMicroelectronics Technology R&D, Director, Partnership Programs. “Consistency between successive generation of projects supported by the EUREKA initiatives JESSI, MEDEA, MEDEA+ and now CATRENE, as well as European Commission supported Programs, enables the development and utilization of successive technology node generations to be optimized.”

FOREMOST used outputs from the EU Sixth Framework Program (FP6) NANOCMOS project, which carried out initial screening and demonstration of appropriate materials, device and interconnect architectures for 45nm CMOS logic. In parallel, PULLNANO, another FP6 project, built upon the successful NANOCMOS project and focused on the early development of 32nm CMOS technology nodes, opening the way to European access to this technology. PULLNANO, successfully concluded at the end of 2008, has been selected as a so-called “STAR” project for the ICT 2010 event to be held September 27-29 2010 in Brussels.