Tanner EDA to demonstrate seamless integration and new features for analog and mixed-signal tools at 43rd Design Automation Conference (DAC)

Designers of analog and mixed-signal chips will halve the time previously required for design capture, simulation, layout, design rule checking and verification. Tanner Tools’ Windows-based interface allows users to start designing in moments, to switch easily among tools and to share files across many locations.

“Today’s analog and mixed-signal designers demand not only functionality but cost efficiency, speed and rapid start-up to maximize the return on their design investment and to minimize time to market,” noted John Tanner, president and CEO, Tanner EDA. “Tanner Tools have evolved from a small number of specialized design aids to today’s complete design solution. Developed to meet the unique needs of analog and mixed-signal circuit designers, the tools are very different from those used by digital designers.”

T-Spice

The essential analog design tool in the Tanner EDA Tool Suite, T-Spice 12.1, offers significant improvements in simulation speed and robustness. It delivers smooth and efficient design flow from schematic to simulation to waveform viewing. T-Spice offers options and commands not found in Berkeley SPICE or most derivatives, such as design optimization, Monte Carlo analysis, multi-dimensional parameters, or source and temperature sweeping. Tightly integrated with Tanner EDA’s S-Edit schematic capture tool, T-Spice provides a state-of-the-art analog design environment at an affordable price.

S-Edit

S-Edit, Tanner EDA’s schematic capture tool, has been completely re-architected and rebuilt into a new tool with user interface, performance and interoperability enhancements added. New is the ability to probe element and sub-circuit terminal currents and charges. S-Edit uses the
TCL scripting language, which makes it fully expandable, as well as enabling easy modification of current designs. Integrated productivity tools, such as Design Checker and Library Browser, plus multiple libraries and language support for English, Chinese, Russian and Japanese, all combine to deliver a comprehensive and interactive design environment.
In addition, S-Edit supports integrated analog simulation with automatic conversion from Cadence® and ViewDraw® schematics. Users can run simulations and cross-probe from S-Edit, making the design process real-time and more efficient. The ability to view operating point simulation results directly on the schematic is another S-Edit productivity enhancing feature.
S-Edit and T-Spice together provide a highly effective front-end design solution.

L-Edit

Designs created in S-Edit, or other schematic-capture tools, can proceed to L-Edit for layout, place and route, and verification. L-Edit performs the physical design with design rules calibrated to the requirements of the chip design and the foundry where the chips will be manufactured. L-Edit adds several key features to improve productivity, to automate tedious manual design tasks and make designing faster. An improved ability to import Virtuoso® language technology files was added along with the layout-versus-layout (LVL) comparison capability. These new capabilities add to L-Edit’s existing schematic driven layout (SDL), which speeds the creation of correct layout from schematics.
Tanner EDA’s HiPer Verify v. 2.1 automates DRC for deep submicron manufacturing. It runs Calibre® and Dracula® rule sets hierarchically and natively, and it tightly integrates into the L-Edit environment, allowing design rule violations to be identified and repaired early before they become a major problem. The new features in HiPer Verify v. 2.1 include significantly improved performance on many layer derivations, DRCs and connectivity-based rules, including electrical rule checking (ERC) for such problems as soft connections or floating wells. New features also include support of Rectangle Enclosure to meet the special requirements for 130 nanometer designs and below.