Qualified IP blocks reduce risk of silicon re-spins
Helping minimise the risk of the need for silicon re-spins for foundry (GDS2) interface customers, ON Semiconductor has made available a qualified IP on its proprietary ONC18 180nm process technology. Minimising the risk of silicon re-spins will therefore help reduce development costs and shorten time-to-market for new designs.
Through its Custom Foundry Business Unit, ON Semiconductor continues to offer new blocks of IP qualified in their proprietary processes developed by various external vendors including Micro Oscillator Inc., Senseeker Engineering Inc., and Silicon Storage Technology, Inc. The ten (10) new IP blocks that have most recently been qualified, provide functions that range from small-pitch column-parallel ADC and cryogenic-compatible LVDS drivers to ultra-low power oscillator and very-small footprint OTP memory. These IP blocks are applicable and beneficial to a wide range of customer end-markets including military/aerospace, medical, consumer, computing, communications, and automotive. In addition to supporting the work of ASIC designers in these sectors, the availability of qualified IP will also help design houses achieve reduced costs and enhanced schedule accuracy in quotations to end customers.
“Working to qualify mixed-signal IP on our leading semiconductor processes is a key part of our strategy to help designers across a wide and diverse range of industry sectors and end applications to shorten time-to-market and reduce development costs for their new products,” said Vince Hopkin, Vice President, Mil/Aero, Digital, Custom Foundry, IPD and Image Sensor Products Division at ON Semiconductor. “Using qualified IP can mitigate the need for costly design re-spins that are sometimes needed to address unforeseen circuit block performance problems or characteristics during the development process and that can critically delay launching products to market.”
Additional IP blocks will be introduced as they are qualified.