Proposal aims to standardise a graph-based test specification

“The Mentor graph-based specification technology brings compelling new value to the verification domain with its capabilities for quickly and exhaustively covering the device state space,” said Peter Jensen, owner and managing director, SyoSil. “This lets us use a unified graph-based description for traditional coverage-driven verification using UVM at the block level, as well as intelligent software-driven verification using embedded C test programs at the system level.”

“Having access to the most advanced functional verification methodologies is essential to maximize electronic design and verification efficiency, and we have seen customers realize a ten-fold gain in productivity through the adoption of graph-based test technology,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “Based on customer feedback, we’re moving forward to recommend and facilitate a standards effort that brings significant benefits to a large number of users, and opens the door to technology innovation.”

Benefits of a Graph-Based Test Specification The benefits of graph-based test specification are threefold. First, it reduces the time spent writing and debugging tests by 50% or more. Verification engineers can use the graph-based specification format to describe the exact same test universes currently described in their existing SystemVerilog UVM constraint-based tests, in less than half the lines of code, without any change to the test intent. This also means a reduction in the number of test bugs, enabling verification engineers to focus on debugging their designs, not their tests.

Second, the graph-based test specification format naturally supports multiple design languages and multiple verification environments enabling re-use across both design context and verification engines. The same graph-based test specification can be used in a SystemVerilog UVM testbench environment for block-level simulation, as well as in an embedded C test program for system-level emulation. It can also be used to generate instructions for microprocessor instruction set verification, and it can even be used on target hardware including FPGA prototyping and post-silicon validation.

Third, the abstract nature of a graph-based test specification lets tool implementations execute the test specification in different ways according to verification requirements. For example, a tool with a graph-based test specification can be instructed to execute the test specification in a systematic way to quickly achieve functional coverage during the early stages of a verification project. At a later time, the tool can be instructed to execute the test specification in a completely random manner to produce soak tests on a simulation farm for regression testing.

Mentor’s Donation to the Graph-Based Test Specification Standards Effort The graph-based specification format is not new to verification. It is based on the standard Backus-Naur Form (BNF), pioneered by IBM, and has been used by many companies to automate compiler testing. Its natural atomic architecture closely mimics the structure of a typical design specification, making requirements mapping easy and straightforward. The graph-based specification format being donated by Mentor Graphics has been augmented to support VLSI design verification across all standard environments and languages including Verilog, VHDL, SystemVerilog, e, SystemC, C/C++, assembly code.