Analysis
Panasonic and Renesas Start Operation of New Development Line for Leading-Edge SoC Process Technologies at the Renesas Naka Site
Panasonic Corporation and Renesas Technology Corp. announced today that they will concentrate their joint development functions for leading-edge SoC process technologies at the Renesas Naka site (in Hitachinaka City, Ibaraki Prefecture) and will start operation of their 28 to 32 nm process development line installed at that site from October 1, 2009. The two companies, by concentrating their joint development functions at the Naka site with its 300 mm wafer line and providing a joint development structure, are developing 28 nm process technologies. They are targeting the start of mass production in the near future.
The In the development line at the Naka site, the two companies have installed new production equipment in addition to having transferred part of the development line equipment from the Renesas Kitaitami site. By carrying out this development in the wafer size that will actually be used in mass production, the two companies are aiming at achieving a smooth transition to mass production and reducing development costs and time. This will improve development and production efficiency.
The 28 to 32 nm SoC process technologies that were the result of these joint development efforts have been applied in SoCs for leading-edge mobile applications and digital appliances from both companies. These products are being mass produced at both companies' sites.
With this long-standing partnership that has fostered the accumulation of earlier technologies leading to the results announced today, both companies are aiming at continued efficient development of leading-edge technologies and the early application of those technologies.