NXP Semiconductors Announces High Speed Converter Interoperability / Interworking with Xilinx FPGAs

The new JESD204A-compliant CGV converters from NXP are suitable for cellular base stations and other wireless communication infrastructure equipment, as well as medical, instrumentation and military/aerospace applications. NXP has developed dedicated CGV ADC and DAC interoperability demo and high performance data acquisition reference design / evaluation boards based on Virtex FPGAs which are available to customers immediately. NXP also offers CGV ADC and DAC demo boards with the FMC interconnect interface for use with Virtex-6 FPGA and Spartan-6 FPGA-based evaluation boards. NXP first publically demonstrated JESD204A CGV data converters interworking with Virtex FPGAs in June 2009 at the IEEE MTT 2009 International Microwave Symposium in Boston. NXP has more than 12 months of JESD204A interworking experience with Xilinx FPGAs, an important consideration for prospective customers.

“NXP Semiconductors is pleased to extend this assured interoperability to our CGV customers, many of whom are interested in using the latest Xilinx FPGAs in their system designs”, said Maury Wood, senior director and product line manager, high speed Converters, NXP Semiconductors. ‘NXP offers several demo boards based on Xilinx Virtex FPGAs which offer clear evidence of this device interoperability. We‘ve also demonstrated interworking during the worldwide Avnet X-fest events beginning in October 2009”, said Wood.

“Through strong collaboration with NXP, we are able to deliver seamless interoperability between our latest FPGA families and NXP‘s data converters”, said Manuel Uhm, director of wireless communications at Xilinx. “Available Xilinx FPGA-based JESD204A reference designs ease the transition from IO limited parallel LVDS based data converters to Serdes-based multi-module high performance data converters while reducing board complexity and system cost,” said Uhm.

CGV™ (Convertisseur Grande Vitesse) designates NXP‘s compliant, superset implementation of the JEDEC JESD204A interface standard, with enhanced rate (4.0 Gbps typical), enhanced reach (100 cm typical), enhanced features (multiple DAC synchronization) and assured FPGA interoperability. Specifically, NXP offers enhancements in terms of transceiver rate (up to 4.0 Gbps versus the standard rate of 3.125 Gbps, a 28% increase), and transmitter reach (up to 100 cm versus the standard reach of 20 cm, a 400% increase). The enhanced CGV features include Multi Device Synchronization (MDS) for the DAC1408D series of D/A Converters, which is not specified, but informatively discussed in the JEDEC specification. NXP has implemented this optional feature to enable LTE MIMO base station and other advanced multi-channel applications. NXP‘s implementation of MDS enables up to sixteen DACs data streams to be sample synchronized and phase coherent.

Virtex®-6 and Spartan®-6 FPGAs provide the programmable silicon foundation for Xilinx® Base-level, Domain-specific, and Market-specific Targeted Design Platforms that enable designers to accelerate innovation and improve differentiation across a wide range of markets and applications. Built for high-performance, compute-intensive applications, Virtex-6 FPGAs deliver over 1Tbps of digital signal processing bandwidth and more than 11Gbps of serial connectivity that is fully scalable and optimized to reduce overall system power consumption. Spartan-6 FPGAs offer an optimal balance of cost, power, and performance that for the first time brings low power and ubiquitous high-speed connectivity to price-sensitive, high-volume markets.