NXP’s New Dual-Core Cortex-M4 and M0 MCU Redefines Digital Signal Control

“The LPC4000 is not just another Cortex-M4. We’re introducing multi-core processing to microcontroller and DSP applications,” said Geoff Lees, vice president and general manager, microcontroller product line, NXP Semiconductors. “Equally important are the configurable peripherals that enable LPC4000 users to reduce the need for external ASIC functionality.”

Microcontroller designers who want more efficient ways to tackle math-intensive algorithms and DSP designers who feel constrained on peripherals stand to benefit from the unique architecture of the LPC4000 family. The LPC4000 is also an excellent fit for designers who want to upgrade from an existing DSC processor.

The NXP LPC4000 family features the following components:

* Cortex-M4 processor. The Cortex-M4 processor combines the benefits of a microcontroller – integrated interrupt control, low power modes, low cost debug and ease of use – with high-performance digital signal processing features such as single-cycle MAC, single instruction multiple data (SIMD) techniques, saturating arithmetic, and a floating point unit.
* Optimized memory architecture. The LPC4000 has an optimized 256-bit wide Flash memory architecture which reduces power consumption with minimum memory fetches while maximizing the performance of the Cortex-M4 processor. The LPC4000 features a dual bank architecture that provides up to 1MB Flash for safe re-programming and flexible memory partitioning. The LPC4000 offers 264 KB SRAM, making it the largest available on any Cortex-M microcontroller.
* Cortex-M0 co-processor. A Cortex-M0 subsystem processor offloads many of the data movement and I/O handling duties that can drain the bandwidth of the Cortex-M4 core. This allows the Cortex-M4 to concentrate fully on crunching numbers for digital signal control applications. Having an asymmetrical dual-core gives developers the power, cost and system complexity savings of a one-chip solution – and allows them to more easily partition their software.
* Unique configurable peripherals. NXP’s unique configurable peripherals available on the LPC4000 include a State Configurable Timer, an SPI Flash Interface, and a Serial GPIO Interface. The State Configurable Timer Subsystem consists of a timer array with a state machine enabling complex functionality including event-controlled PWM waveform generation, ADC synchronization, and dead-time control. The SPI Flash Interface provides a seamless high-speed memory-mapped connection to virtually all SPI and quad-SPI manufacturers. NXP’s Serial GPIO, available for the first time on the LPC4000, allows a developer the flexibility to interface to any non-standard serial interface or to mimic multiple standard serial interfaces (such as I2S, TDM for multi-channel audio, I2C and more). Additional peripherals on certain members of the family include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware-enabled TCP/IP checksum calculation, and a high-resolution color LCD controller.
* Standard features. Standard features on all members of the LPC4000 family include 32 KB ROM containing boot code and on-chip software drivers, AES-128 decryption (encryption is available on some members of the family), eight-channel General-Purpose DMA (GPDMA) controller, two 10-bit ADCs and 10-bit DAC with data conversion rate of 400k samples/s, a motor Control PWM and Quadrature Encoder Interface, 4 UARTs, 2 Fast-mode Plus I2C, I2S, 2 SSP/SPI, smart card interface, 4 timers, windowed watchdog timer, an alarm timer, an ultra-low power RTC with 256 bytes of battery powered backup registers, and up to 146 general purpose I/O pins.