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MOSIS adds 0.25 micron SiGe BiCMOS technology multi-project wafer (MPW) fabrication

4th July 2007

ES Admin

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MOSIS, a provider of low-cost prototyping and small volume production services for custom ASICs, announces availability of the IBM 0.25 micron SiGe BiCMOS 6WL technology. Utilising the service gives ASIC designers access to this advanced technology at less than 10% of the cost of a dedicated wafer run, minimizsing up-front risk and costs. The process is suited to high-performance analogue chip design for consumer wireless applications including mobile phones, WLAN, and global positioning devices. It has 5 metal layers and supports metal-insulator-metal (MiM) capacitors. The top two thick metals can be used to make inductors. Supply voltages are 2.5V for the core and 3.3V for I/O. IBM’s flip chip bumping (C4) is subject to availability at additional cost.

Design kits that encompass IBM’s design rules, process specifications, SPICE parameters and cell libraries are available. The first MPW run based on this technology is provisionally scheduled for the end of August 2007.

Deputy Director of MOSIS, Wes Hansford, commented, “The more advanced the technology, the higher the chance of designs needing at least one re-spin. Costs can escalate out of control if dedicated wafer runs are used at every step. Shared wafer services dramatically reduce risks and cost, while often reducing overall development time too. Companies designing chips can quickly get samples into the hands of their customers while the devices are being fine-tuned for later volume production runs. This flexibility is particularly important in consumer electronics, where product life cycles are continuing to shrink and time-to-market is a critical success factor.”

In Europe, the MOSIS service is exclusively available through EDA Solutions Ltd.