Mentor Graphics Calibre PERC Programmable Electrical Rule Checker Improves Fujitsu Chip Reliability

According to Masaru Ito, Director of System LSI Technology & Product Department, Technology Development Division, IP & Technology Development and Manufacturing Unit at Fujitsu Semiconductor Limited, “In the past we have used a combination of visual layout inspection and custom scripts to find issues associated with circuitry to protect against ESD events and to support multiple voltage domains. Of course, this was very time consuming and not very reliable. We found the combination of features in Calibre PERC combined with its extensive programmability allowed us to define and perform all the checks we need to make, and it gives us the flexibility we need to adapt to future requirements. Initially, we are using Calibre PERC for a part of our design technology, and in the future we will expand usage to all IC development in order to improve overall product reliability and verification efficiency.”

“Calibre PERC gives IC designers a new tool to address reliability challenges by assessing critical circuits both geometrically and electrically, while greatly reducing the manual time and effort required for verification,” said Joseph Sawicki, Vice President and General Manager of Mentor’s Design-to-Silicon division. “Its programmability also gives PERC a unique ability to adapt to multi-voltage, mixed-signal environments and continue to grow with customer needs.”