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Lattice Semiconductor Plans SRIO Interoperability With Cavium Networks’ Octeon II Processors

12th May 2010

ES Admin

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Lattice Semiconductor Corporation announced plans to interoperate between Cavium Networks’ OCTEON II CN63XX processors and the LatticeECP3™ FPGA family via a Serial Rapid IO (SRIO) Specification 2.1 link. SRIO is commonly used in 3G/4G wireless base stations and wireline switches and routers where low latency is critical. Cavium’s OCTEON II processor incorporates two to six cnMIPS64® cores, the most advanced third generation hardware acceleration, and SERDES-based I/Os, including SRIO. Lattice’s ECP3 device boasts the lowest power in a mid-range FPGA family, rich memory density, DSP blocks and SERDES I/Os capable of supporting SRIO.

Cavium and Lattice have already begun executing their plan to demonstrate SRIO interoperability, and both companies will announce updates as they become available. “The addition of the SRIO interface in the OCTEON II processors, along with the wide variety of other standards-based interfaces, provides a new low-latency connectivity option,” said Tasha Castañeda, Senior Strategic Alliance Manager, Cavium Networks. “We are pleased to add Lattice to Cavium’s PACE (Partnership to Accelerate Customer End-solutions) ecosystem in order to offer our customers a strong FPGA design solution.”

“Lattice is excited to be working with Cavium Networks. This SRIO interoperability testing will strengthen our rich portfolio of wireless IP. We are working to introduce future bridging applications for the OCTEON II and our ECP3 family, including SRIO to CPRI, SRIO to PCIe and SRIO to SGMII,” said Ted Marena, Director of Business Development for Lattice.