International conference will tackle the impact of CMOS variability on the semiconductor industry

‘Design for variability’ will bring together world leading companies representing the complete semiconductor supply-chain and major research initiatives in order to analyse the far-reaching implications of variability on semiconductor design and to promote collaboration between industry players.

Derek Boyd, CEO of NMI said, “The effects of CMOS variability will be felt throughout the industry as it extends backwards into the design chain and forwards into applications. Chip architects will need to have a good understanding of how variability affects system design and companies of all sizes, especially SMEs, must now look ahead and think how they are going cope with the issues”.

He continued, “The issue of variability is no longer the preserve of the IDMs and together with world experts, we simply have to raise awareness of the real challenges that are being faced throughout the industry and to encourage further industry collaboration to help find solutions.”

Dr Asen Asenov, The University of Glasgow’s leader of the nanoCMOS project and the keynote speaker at the conference added, “65nm technology is relatively easy to work with, however at 45nm and below, significant variability is introduced which adversely affect the yield, reliability and power consumption of digital circuits. SRAM for example has been identified as one of the first potential casualties and will have a serious impact on SoC and other products.”

He added, “Put simply, designers will need to learn how to design reliable systems on unreliable technology, tool providers will need to switch from a deterministic to a more statistical approach and as design margins continue to decrease, foundries will need to change from providing design rules to supplying design models. Variability is a major issue that needs to be fully addressed. This conference is intended to do just that.”

Dr Asenov’s opening keynote address entitled “Variability in next generation CMOS technologies and impact on Design” will be followed by four speaker sessions:
Session 1: ‘Design Concepts’ (IMEC, University of Manchester and STARC)
Session 2: ‘Design implementation & tools’ (Mentor Graphics, Synopsys and Cadence.)
Session 3: ‘Semiconductor Technologies’ (IBM, Freescale and TSMC.)
Session 4: ‘IP Development & Research’ (ARM)

These sessions will then be followed by a panel debate entitled, “Integration and Collaboration in the Era of Design for Variability (DfV)”.

In addition to the main conference, delegates are also offered the opportunity to attend two complementary satellite events organised by Dr Asenov. Consisting of half-day reviews, the events will introduce delegates to the research highlights from two major multidisciplinary UK research projects in the fields of device, circuit and system design.

Taking place on 22 October, “Meeting the material challenges of nano-CMOS electronics” will summarise state of the art research in materials modelling and electrical device simulations. And on 24 October, the UK eScience pilot project “Meeting the design challenges of nano-CMOS electronics” will present developments in multiscale and grid enabled TCAD and ECD device simulation.