EDA tool vendor selected for advanced node chip design

For GF, establishing Cadence as its primary vendor has enabled them to improve engineering productivity.

Avera Semi has successfully completed several large, complex 12 and 14nm tapeouts and delivered production designs using Cadence flagship solutions such as the Innovus Implementation System, the Genus Synthesis Solution, the Tempus Timing Signoff Solution and Xcelium Parallel Logic Simulation as well as the Virtuoso custom IC design platform, Spectre circuit simulation platform and Allegro and Sigrity tools, which are part of following product categories:

• Digital and Signoff: The parallelised, integrated Cadence digital and signoff solutions provided Avera Semi with a trusted design flow to achieve industry-leading power, performance and area (PPA) results with integrated signoff accuracy for designs with more than 500M instances, complex clocking requirements and chip sizes at the mask reticle limit.
• System and Verification: The Cadence Verification Suite helped the Avera Semi verification team find bugs more efficiently, quickly implement and bring up complex testbenches for faster project completion and fuel testbench automation, analysis and reuse for increased productivity.
• Custom IC/Analog Design: The comprehensive analog and mixed-signal simulation capabilities in the Cadence custom IC design platform enabled Avera Semi to consistently, accurately and quickly design and verify complex IP such as the Avera Semi 112G Serial Link. Additionally, the tight integration of Cadence physical verification and design-for-manufacturing (DFM) tools within the Cadence Virtuoso IC design platform accelerated design and implementation.
• PCB Design and Analysis: Cadence’s PCB design and analysis tools helped Avera Semi achieve a smooth and efficient interface between the chip and packaging teams, helping to manage and track engineering change requests. The tool customisability enabled Avera Semi to automate the numerous properties associated with a package, reducing manual errors and design cycle time.

Kevin O’Buckley, GM at Avera Semi, stated: “Today’s announcement is another solid step in our collaborative journey to achieve a higher level of productivity through Cadence’s design flow. We have already deployed the Cadence flows to complete a number of successful production designs for our customers using the GF 12nm and 14nm FinFET process technologies and will extend our collaboration with Cadence on advanced nodes. 

“Standardising on Cadence’s custom, digital and IC package flows and verification solutions will help us master new challenges encountered at advanced nodes and expand our leadership in designs for data centres, wired communications, and machine learning and artificial intelligence applications.”

Dr Chin-Chi Teng, Senior Vice President and General Manager of the Digital & Signoff Group at Cadence, added: “Avera Semi uses Cadence as its primary supplier due to many years of successful collaborations on large, complex designs that met evolving market demands. 

“We are always working to optimise design flow speed, throughput and provide differentiated tool features to deliver best-in-class PPA to customers. As we expand upon our longstanding relationship with Avera Semi, their customers can also benefit from our continued innovation and dedication to advancing ASIC design.”