Analysis
ARM and Cadence Achieve Industry Milestone with Tape Out of 20nm ARM Cortex-A15 MPCore Processor
ARM and Cadence Design Systems, Inc. announced the tape out of the industry’s first 20nm design based on the ARM Cortex-A15 MPCore processor. The test chip, targeting TSMC’s 20nm process, was jointly developed by engineers from ARM, Cadence and TSMC using a Cadence RTL-to-signoff flow. Today’s milestone announcement is the result of an 18 month collaboration between ARM and Cadence on optimised design flows for the Cortex-A15 processor.
“T“The Cortex-A15 processor implementation targeting the TSMC 20nm process pushed the envelope on all fronts and required engineers from ARM, Cadence and TSMC to work as a seamless team,” said Chi-Ping Hsu, Senior Vice President, Research and Development, Silicon Realization Group at Cadence. “We have made significant 20nm developments in the last three years in our Virtuoso® and Encounter® design and sign-off solutions for the world’s most advanced processes. This important collaboration milestone enables customers to design Cortex-A15 processor-based designs at the most advanced process nodes. We intend to expand this collaborative model in working with ARM on the Cortex-A15 and other processor development.”
“TSMC has been working very closely with its OIP ecosystem partners to ensure continued customer success in the fast-growing markets,” said Suk Lee, Director, Design Infrastructure Marketing Division at TSMC. “The tape out of this ARM Cortex-A15 processor is another good example of closer and tighter collaboration between TSMC and its ecosystem partners such as ARM and Cadence.”
ARM and Cadence recently signed a multi-year technology agreement that will provide ARM engineering teams with ongoing access to Cadence products. ARM and Cadence are working to ensure that both the ARM processors and the Cadence design flows are optimised to work together. This provides a significant technology benefit to ARM Partners, who will have access to flows optimised as part of ARM processor development.