Coresonic founders present fully programmable baseband processor for mobile WiMAX and DVB-T/H at ISSCC

This week at the International Solid State Circuits Conference in San Francisco, CA, USA, two of the founders of Coresonic AB will present the architecture of its fully programmable baseband processor which enables standards such as mobile WiMAX and DVB-T/H to be implemented much more efficiently than fixed function circuits. The paper will outline the characteristics of the processor’s SIMT (Single Instruction stream Multi-Task) architecture and its benefits over conventional SIMD and VLIW techniques, and demonstrate an example of its implementation in a complete DVB-T/H receiver system with measured results.

The authors of the paper, from the Linköping University in Sweden, are also co-founders of Coresonic along with Dr Eric Tell and Professor Christer Svensson and have now applied this architecture in a commercial environment. Professor Dake Liu, one of the authors and also CTO of Coresonic, commented, “As we will outline in the paper, in a laboratory environment, without any specific power management circuits, we were able to implement a fully programmable baseband processor in less than 11mm2 in a 0.12μm CMOS process and achieve 70mW at 70MHz at the highest data rate of 31.67Mb/s in DVB-T/H. In a commercial environment, with power management sub-systems added, we have used this architecture to significantly improve the power consumption and make it highly competitive compared to other implementations of wireless baseband processors.”

A key part of the baseband processor presented is the SIMT architecture developed by the authors. This exploits the characteristics of baseband algorithms to reduce the control overhead and improve the memory utilization compared to VLIW/SIMD-based baseband processors. The LeoCore technology from Coresonic is based on this processor architecture, and uses vector instructions that operate on large data-sets in SIMD execution units. The key idea is to issue only one instruction each clock cycle but still allow several operations to execute in parallel as vector instructions may run for several clock cycles on the SIMD units. Using this technique, memory efficiency is high and an entire DVB-T/H implementation fits within the program memory of 2kwords.

In addition, programmability of the processor enables hardware reuse not only between different radio standards but also between different parts of the processing flow. Through hardware multiplexing a programmable solution can reach smaller silicon area than a hardwired solution even for a single standard. Smaller silicon also results in lower power consumption due to reduced leakage and on-chip communication power.

Coresonic CEO Rick Clucas commented, “I am very proud of the work done by the founders of the company at the university – particularly as they were able to show that even a pure research project with the back end layout being done by Anders could achieve results as good as the best solutions available today for DVB-T. Since then, Coresonic has been able to significantly optimize the architecture to produce even better results.” He added, “What’s more, because of the scalability of the architecture we are able to tackle 4G standards such as WiMax and LTE with very similar numbers. Because our results are so efficient, companies can choose to implement the technology in cheaper technologies or at very low voltages – enabling them to make the best design trade-offs for their end products.”