Cadence Drives Giga-gate/Gigahertz Design at 28nm with New Digital End-to-end Flow

Working seamlessly with Cadence’s analog/mixed-signal and silicon/package co-design domains, the new digital 28-nanometer flow enables designers to consider the entire chip flow holistically to drive breakthroughs in high-performance, low-power, mixed-signal, and even 3D-IC designs- critical success factors for mobility-based and multimedia SoCs.

The new flow, available immediately, supports Cadence’s approach to Silicon Realization through its focus on unique and pervasive design intent, abstraction, and convergence from RTL to GDSII, then through to packaging. Silicon Realization is a key element of the EDA360 vision.

Eliminating the need for tradeoffs between complexity and advanced process nodes, the new flow optimizes complex design at 28 nanometers, providing a path for advanced SoC development to realize the cost benefits of smaller geometries. Key to the flow’s performance (add link to Wei Lii’s blog) is a unified digital design, implementation, and verification based on intent, abstraction, and convergence.

Features that enhance unified intent include:

· Complete, silicon-proven 28-nanomter design rule intent (electrical, physical, DFM) with early, upfront tradeoff analysis, and a 2x improvement in routing runtime through intelligent via and pin-density optimizations

· Early clock topology intent capture and planning that uses physical information to intelligently optimize clock gating and balance clock trees throughout the design during synthesis

Features that enhance abstraction include:

· Breakthrough data abstraction technologies that enable entire blocks of logic to be modeled simply and accurately, and optimized across logical and physical domains, for giga-gate scalability and design productivity

· Support for hierarchical low-power and OpenAccess-based mixed-signal quick/detailed abstractions to enable rapid integration of IP and advanced SoCs

Faster convergence is achieved through such features as:

· A physically aware pre-mask functional ECO capability that automates difficult to implement functional ECOs, providing faster convergence and dramatically shortening the design cycle.

· A breakthrough architecture for in-design advanced analysis that provides ultra fast one-step signal integrity and timing analysis closure during the design flow for efficient design convergence

· Accurate full mixed-signal static timing analysis and timing-driven optimization to reduce iterations between analog and digital design teams

And new fully-integrated 3D-IC capabilities with unified intent, abstraction, and convergence spanning digital, full-custom, and package design, now enable optimized performance, size, cost and power.

“The complexity of 28-nanometer design coupled with the need to support complex giga-gate/gigahertz requirements demands an integrated end-to-end flow,” said David Desharnais, senior director, Silicon Realization product marketing. “Our unique Silicon Realization approach allows our customers to push their SoC designs to new levels in order to deliver the highest performance silicon for multimedia, communications and computing applications. Today’s announcement of our comprehensive 28-nanometer digital Silicon Realization flow continues our push toward realizing the EDA360 vision.”

The Encounter-based Silicon Realization digital end-to-end flow includes technologies such as Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Conformal technologies, Encounter Test, Encounter Timing System, Cadence QRC Extraction, Encounter Power System and Encounter DFM technologies.