Altera Accelerates FPGA Design Productivity in Quartus II Software Version 10.1 with Next-Generation System-Integration Tool

Qsys enables high-performance FPGA-based system design through the use of a network-on-chip-based interconnect architecture. Qsys applies network theory to on-chip communications that provide performance improvements over conventional bus and switch fabric interconnections. This approach, which packetizes all memory-mapped and streaming data, delivers higher operating frequency for the same latency and resource utilization. Qsys also offers an automatic pipelining feature to further increase system fMAX.



Designs that include a high number of intellectual property (IP) or system components benefit from the hierarchical design flow featured within Qsys. The tool enables system scalability by dividing large FPGA designs into multiple sub-systems. This hierarchy allows designers to easily manage each sub-system while giving them the ability to add additional sub-systems to the design with minimal impact on system performance.



Qsys broadens the amount of IP available for FPGA-based system-level design through support for industry-standard interfaces, such as Avalon and AMBA AXI and AHB standards from ARM. The tool provides designers ultimate flexibility by automatically handling the bridging between multiple interface standards. This capability enables users to leverage IP cores with multiple interfaces in a single design. The initial release of Qsys supports the open-standard Avalon interface. Additional industry-standard interfaces, such as AMBA AXI and AHB standards from ARM, will be supported in future releases. For more information about Qsys, visit www.altera.com/qsys.



“Productivity continues to be at the forefront of our customers' minds,” said Chris Balough, senior director of software, embedded, and digital signal processing (DSP) marketing at Altera. “Altera's new Qsys tool leverages our decade-long experience as the pioneer in FPGA-based switch fabrics to deliver a substantial level of new capabilities and performance that will improve customers' system-level design and IP reuse.”



Expanded ModelSim OEM Agreement and Simulation Support



Altera recognizes the importance simulation plays in the FPGA design process and continues to improve the simulation experience within the Quartus II software design environment with the latest release. Altera recently renewed its multi-year OEM agreement with Mentor Graphics, which provides Quartus II software customers access to the latest version of the ModelSim® tool. New features in the ModelSim-Altera edition and ModelSim-Altera starter edition include a waveform editor and improved Altera® IP simulator support. Waveform editing supports a popular method to quickly generate input stimulus for verification. Additional Features Within Quartus II Software v10.1 Include:



* New Device Support—This release provides complete support for Altera's new MAX® V CPLD device family announced today. Also added is support for Altera's new Arria® II GZ FPGA family and expanded support for the Stratix® V FPGA family.

* Faster Recompiles—Enhancements to the software's Rapid Recompile feature maximize designer productivity by reducing compilation time by 65 percent, on average.

* New External Memory Interface Toolkit—The new toolkit helps designers bring their boards up faster by identifying calibration issues and measuring the margins for each DQ strobe (DQS) signal.

* Enhancements to Chip Planner and TimeQuest—Chip Planner includes a new window to let designers easily view and trace multiple critical timing paths. TimeQuest adds a new capability to report timing closure recommendations so designers can quickly and easily identify and resolve timing closure issues.