Agilent Technologies to Showcase Bit Error Ratio Tester at OFC/NFOEC

A new era of data-center infrastructure enabling cloud computing, big data and analysis is driving the development of new high-speed data transfer standards such as 100-Gb Ethernet and 32-Gb Fibre Channel. The higher speeds create new testing challenges for designers of servers, network interface cards, backplanes and communication ICs. That’s because quality degrades when signals are transmitted over backplanes, printed circuit board traces and long cables.

To address the issue, Agilent has created remotely mountable pattern-generator heads for use with its N4960A BERTs (bit error ratio testers). The new pattern-generator heads (N4951B Option D32 and Option D17) feature integrated four-tap de-emphasis (one pre-cursor, two post-cursors) operating up to 32 Gb/s, which provides designers with the signal compensation required for transmitter emulation when they characterize receivers and systems.

In addition, N4980A multi-instrument BERT software allows engineers to directly compute de-emphasis tap weights from the frequency response (s-parameters) of their signal paths. Designers can easily optimize tap weights in the tool and program them directly into the pattern generator head when they are ready.

“We are the first in the industry to provide de-emphasis functionality operating up to 32 Gb/s,” said Juergen Beck, vice president and general manager of Agilent’s Digital Photonics Test Division. “With this capability added to the N4960A serial BERT family, high-speed backplane and communication IC designers now have the signal fidelity and signal compensation tools they need to test their next-generation devices.”

As part of the N4960A BERT family, the new pattern generators are configured as remote heads connected to the BERT controller with a one-meter control cable. This configuration allows the pattern generator to be located close to the device under test, minimizing the length of the signal cable, which helps minimize signal degradation.