Oasys Design Systems announced today that register retiming capability for improved quality of results is now available in the Oasys RealTime synthesis engine. The Oasys RealTime synthesis engine is the core technology of the Oasys RealTime Explorer and Designer products, the only EDA tools that produce the same implementation accurate results for RTL exploration and physically-aware synthesis.

Oasys Design Systems revealed today that it has joined the TSMC Soft-IP Alliance Program to enable TSMC IP partners with a new RTL exploration tool to improve quality of results and reduce the iterations required for design closure.

Oasys Design Systems today announced that its Chip Synthesis platform, in use in production environments, now includes design for test (DFT) capabilities, further extending the fast speed and high capacity of Oasys’ RealTime Designer software.

Oasys Design Systems today unveiled the latest version of its revolutionary Chip Synthesis platform with enhanced capabilities that include chip-level power analysis and the ability to re-synthesize a design from the register transfer level (RTL) with new power constraints.

Gary Meyers, an experienced electronic design automation (EDA) and semiconductor executive, has been named to the Board of Directors of Oasys Design Systems, provider of Chip Synthesis™, a fundamental shift in how synthesis is applied to integrated circuit (IC) design and implementation.

Oasys Design Systems announced today that Craig Robbins, a noted electronic design automation executive, has assumed the role of senior vice president of sales, reporting to Paul van Besouw, Oasys’ president and chief executive officer.

Oasys Design Systems announced today that it has added support for SystemVerilog to RealTime Designer™, its revolutionary new Chip Synthesis platform used in production flows at leading-edge semiconductor and systems companies worldwide.

Verific Design Automation, supplier of de facto standard front-end software to the EDA and semiconductor community, announced today that Oasys Design Systems has expanded its relationship by licensing Verific’s SystemVerilog front-end software for RealTime Designer™. Previously, Verific licensed its VHDL analyzer to Oasys. As a result, design teams using RealTime Designer, Chip Synthesis™ software capable of synthesizing register transfer...

Oasys Design Systems today announced its multi-year strategic licensing agreement with Xilinx for Oasys’ revolutionary Chip Synthesis™ technology. The companies are not disclosing terms of the agreement or details regarding Xilinx’s long-term plans for implementing the technology for field programmable gate array (FPGA)-based design.

Oasys Design Systems today announced that Juniper Networks® has selected RealTime Designer™, a revolutionary new Chip Synthesis™ platform, for the design of its next-generation networking chips. “After a thorough evaluation, we determined that RealTime Designer offers high-quality results and performs very well in our environment,” said Debashis Basu, vice president for Silicon Development at Juniper Networks. “It is a great tool tha...